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PDF 25AA040 Data sheet ( Hoja de datos )
| Número de pieza | 25AA040 | |
| Descripción | 4K SPI Bus Serial EEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 25AA040 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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Not recommended for new designs –
Please use 25AA040A or 25LC040A.
25AA040/25LC040/25C040
4K SPI Bus Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
25AA040
25LC040
25C040
1.8-5.5V
2.5-5.5V
4.5-5.5V
1 MHz
2 MHz
3 MHz
Temp.
Ranges
I
I
I,E
Features:
• Low-power CMOS technology:
- Write current: 3 mA, typical
- Read current: 500 μA, typical
- Standby current: 500 nA, typical
• 512 x 8-bit organization
• 16 byte page
• Write cycle time: 5 ms max.
• Self-timed Erase and Write cycles
• Block write protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in write protection:
- Power on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential read
• High reliability:
- Endurance: 1M cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP, SOIC and TSSOP packages
• Temperature ranges supported:
- Industrial (I):
-40°C to +85°C
- Automotive (E) (25C040): -40°C to +125°C
Description:
The Microchip Technology Inc. 25AA040/25LC040/
25C040 (25XX040*) is a 4 Kbit serial Electrically
Erasable PROM. The memory is accessed via a simple
Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS)
input.
*25XX040 is used in this document as a generic part number
for the 25AA040/25LC040/25C040 devices.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts. Also, write operations to the device can be
disabled via the write-protect pin (WP).
Package Types
PDIP CS 1
8 VCC
SO 2
WP 3
7 HOLD
6 SCK
VSS 4
5 SI
SOIC
CS 1
SO 2
WP 3
VSS 4
TSSOP
HOLD
VCC
CS
SO
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
8 SCK
7 SI
6 VSS
5 WP
Block Diagram
STATUS
Register
HV Generator
I/O Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
SI
SO
CS
SCK
HOLD
WP
VCC
VSS
Y Decoder
Sense Amp.
R/W Control
© 2006 Microchip Technology Inc.
DS21204E-page 1
1 page  
25AA040/25LC040/25C040
TABLE 1-3: AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V
—
VHI = VCC - 0.2V
(Note 1)
VHI = 4.0V
(Note 2)
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
FIGURE 1-4:
AC TEST CIRCUIT AC
VCC
2.25 KΩ
SO
1.8 KΩ
100 pF
© 2006 Microchip Technology Inc.
DS21204E-page 5
5 Page 
25AA040/25LC040/25C040
3.7 Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
• The write enable latch is reset when the WP pin is
low
3.8 Power-On State
The 25XX040 powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A low level on CS is required to enter active state
TABLE 3-3:
WP
Low
High
High
WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
Protected Blocks
Unprotected Blocks
X Protected
0 Protected
1 Protected
Protected
Protected
Writable
STATUS Register
Protected
Protected
Writable
© 2006 Microchip Technology Inc.
DS21204E-page 11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 25AA040.PDF ] | |
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