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PDF FSL176MRT Data sheet ( Hoja de datos )
| Número de pieza | FSL176MRT | |
| Descripción | Green Mode Fairchild Power Switch | |
| Fabricantes | Fairchild Semiconductor | |
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August 2012
FSL176MRT
Green-Mode Fairchild Power Switch (FPS™)
Features
Advanced Soft Burst-Mode Operation for
Low Standby Power and Low Audible Noise
Random Frequency Fluctuation for Low EMI
Pulse-by-Pulse Current Limit
Various Protection Functions: Overload Protection
(OLP), Over-Voltage Protection (OVP), Abnormal
Over-Current Protection (AOCP), Internal Thermal
Shutdown (TSD) with Hysteresis, Output-Short
Protection (OSP), and Under-Voltage Lockout (UVLO)
with Hysteresis
Low Operating Current (0.4mA) in Burst Mode
Internal Startup Circuit
Internal High-Voltage SenseFET: 650V
Built-in Soft-Start: 15ms
Auto-Restart Mode
Description
The F SL176MRT is an
integrated Pulse W idth
Modulation (PWM) controller and SenseFET specifically
designed for offline Sw itched-Mode Power Supplies
(SMPS) with minimal external components. T he PW M
controller includes an in
tegrated fixed-frequency
oscillator, Under-Voltage Lockout (UVLO), Leading-
Edge Blanking (LEB), optimized gate driver, internal
soft-start, temperature-co mpensated precise current
sources for loop compensation, and self-protection
circuitry. Compared with a discrete MOSF ET and PW M
controller solution, the F SL176MRT can reduce total
cost, component count, size, and w eight; w hile
simultaneously increasing efficiency , productivity , and
system reliability. T his device provides a basic platform
for cost-effective design of a flyback converter.
Applications
Power Supply for LCD Monitor, STB, and
DVD Combination
Ordering Information
Part Number
Output Power Table(2)
Package
Operating
Junction
Temperature
Current
Limit
RDS(ON)
(Max.)
230VAC ±15%(3)
Adapter(4)
Open
Frame(5)
85~265VAC
Adapter(4)
Open
Frame(5)
Replaces
Device
TO-220
FSL176MRTUDTU
6-Lead(1)
U-
Forming
-40°C ~
+125°C
3.50A 1.6Ω
80W
90W
48W
70W FSGM0765R
Notes:
1. Pb-free package per JEDEC J-STD-020B.
2. The junction temperature can limit the maximum output power.
3. 230V AC or 100/115VAC with voltage doubler.
4. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature.
5. Maximum practical continuous power in an open-frame design at 50C ambient temperature.
© 2012 Fairchild Semiconductor Corporation
FSL176MRT • Rev. 1.0.0
www.fairchildsemi.com
http://www.Datasheet4U.com
1 page  
Electrical Characteristics
TJ = 25C unless otherwise specified.
Symbol Parameter
SenseFET Section
BVDSS Drain-Source Breakdown Voltage
IDSS Zero-Gate-Voltage Drain Current
RDS(ON) Drain-Source On-State Resistance
CISS Input
Capacitance(12)
COSS Output
Capacitance(12)
tr Rise
Time
tf Fall
Time
td(on) T urn-On Delay
td(off) T urn-Off Delay
Control Section
fS Switching Frequency(12)
fS Switching Frequency Variation(12)
DMAX Maximum Duty Ratio
DMIN
Minimum Duty Ratio
IFB Feedback Source Current
VSTART
VSTOP
UVLO Threshold Voltage
tS/S Internal Soft-Start Time
Burst-Mode Section
VBURH
VBURL Burst-Mode Voltage
VHys
Protection Section
ILIM
VSD
IDELAY
tLEB
VOVP
tOSP
VOSP
tOSP_FB
TSD
THys Hy
Peak Drain Current Limit
Shutdown Feedback Voltage
Shutdown Delay Current
Leading-Edge Blanking Time(12)(14)
Over-Voltage Protection
Output-Short
Protection(12)
Threshold Time
Threshold VFB
VFB Blanking Time
Thermal Shutdown Temperature(12)
Conditions
VCC = 0V, ID = 250A
VDS = 520V, TA = 125C
VGS=10V, ID =1A
VDS = 25V, VGS = 0V, f=1MHz
VDS = 25V, VGS = 0V, f=1MHz
VDS = 325V, ID = 4A, RG=25Ω
VDS = 325V, ID = 4A, RG=25Ω
VDS = 325V, ID = 4A, RG=25Ω
VDS = 325V, ID= 4A, RG=25Ω
VCC = 14V, VFB = 4V
-25C < TJ < 125C
VCC = 14V, VFB = 4V
VCC = 14V, VFB = 0V
VFB=0V
VFB = 0V, VCC Sweep
After Turn-On, VFB = 0V
VSTR = 40V, VCC Sweep
VCC = 14V, VFB Sweep
di/dt = 300mA/s
VCC = 14V, VFB Sweep
VCC = 14V, VFB = 4V
VCC Sweep
OSP Triggered when
tON<tOSP & VFB>VOSP
(Lasts Longer than tOSP_FB)
Shutdown Temperature
steresis
Min. Typ.
650
1.3
674
93
30
26
16
39
61 67
±5
61 67
65 90
11 12
7.0 7.5
15
0.39 0.45
0.26 0.30
150
3.15 3.50
6.45 7.00
1.2 2.0
300
23.0 24.5
0.7 1.0
1.8 2.0
2.0 2.5
130 140
60
Max.
250
1.6
73
±10
73
115
13
8.0
0.51
0.34
3.85
7.55
2.8
26.0
1.3
2.2
3.0
150
Unit
V
A
Ω
pF
pF
ns
ns
ns
ns
kHz
%
%
%
A
V
V
ms
V
V
mV
A
V
A
ns
V
s
V
s
C
C
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation
FSL176MRT • Rev. 1.0.0
5
www.fairchildsemi.com
5 Page 
4.3. Output-Short Prote ction (OSP) : If the output is
shorted, steep current with extremely high di/dt can
flow through the SenseFET during the minimum turn-
on time. Such a steep current brings high-voltage
stress on the drain of the SenseFET when turned off.
To protect the device from this abnormal condition,
OSP is included. It is comprised of detecting VFB and
SenseFET turn-on time. W hen the VFB is higher than
2.0V and the SenseF ET turn-on time is low er than
1.0μs, the F SL176MRT recognizes this condition as
an abnormal error and shuts dow n PW M sw itching
until VCC reaches VSTART again. An abnormal condition
output short is shown in Figure 22.
5. Soft Burst-Mode Operation : T o minimize pow er
dissipation in Standby M ode, the F SL176MRT enters
Burst-Mode operation. As the load decreases, the
feedback voltage decreases. The device automatically
enters Burst Mode w hen t he feedback voltage drops
below V BURL (300mV), as show n in F igure 23. At this
point, sw itching stops and t he output voltages start to
drop at a rate dependent on standby current load. T his
causes the feedback voltage to rise. Once it passes
VBURH (450mV), switching resumes. T he feedback
voltage then falls and the pr ocess repeats. Burst Mode
alternately enables and dis ables sw itching of the
SenseFET, reducing switching loss in Standby Mode.
Figure 22. Output-Short Protection
4.4 Ov er-Voltage Pro tection (OVP): If the
secondary-side feedback circuit malfunctions or a
solder defect causes an opening in the feedback path,
the current through the
opto-coupler transistor
becomes almost zero. Then VFB climbs up in a similar
manner to the overload situat ion, forcing the preset
maximum current to be supplied to the SMPS until the
overload protection is triggered. Because more energy
than required is provided to the output, the output
voltage may exceed the ra ted voltage before the
overload protection is tri ggered, resulting in the
breakdown of the devices in the secondary side. T o
prevent this situation, an O VP circuit is employed. In
general, the V CC is proportional to the output voltage
and the F SL176MRT uses VCC instead of directly
monitoring the output voltage. If VCC exceeds 24.5V,
an OVP circuit is triggered, resulting in the termination
of the sw itching operat ion. T o avoid undesired
activation of OVP during normal operation, VCC should
be designed to be below 24.5V.
4.5 Thermal Shutdow n (TSD) : The SenseF ET and
the control IC on a die in one package makes it easier
for the control IC to detec t high temperature of the
SenseFET. If the temperature exceeds ~ 140C, the
thermal shutdow n is triggered and stops operation.
The F SL176MRT operates in auto-restart mode until
the temperature dec reases to around 75 C, w hen
normal operation resumes.
Figure 23. Burst-Mode Operation
6. Ra ndom Fre quency Fluctuation (RFF): Fluctuating
switching frequency of an SMPS can reduce EMI by
spreading the energy over a wide frequency range. T he
amount of EMI reduction is directly related to the
switching frequency variation, which is limited internally.
The switching frequency is determined randomly by the
external feedback voltage and an internal free-running
oscillator at every sw itching instant. T his random
frequency fluctuation scatters the EMI noise around
typical switching frequency (67kHz) effectively and can
reduce the cost of the input filter in cluded to meet the
EMI requirements (e.g. EN55022).
© 2012 Fairchild Semiconductor Corporation
FSL176MRT • Rev. 1.0.0
Figure 24. Random Frequency Fluctuation
www.fairchildsemi.com
11
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet FSL176MRT.PDF ] | |
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