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PDF 24LC61-SN Data sheet ( Hoja de datos )

Número de pieza 24LC61-SN
Descripción 1K/2KSoftwareAddressableI2CSerialEEPROM
Fabricantes MicrochipTechnology 
Logotipo MicrochipTechnology Logotipo



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No Preview Available ! 24LC61-SN Hoja de datos, Descripción, Manual

M 24LCS61/24LCS62
1K/2K Software Addressable I2CSerial EEPROM
PRODUCT OFFERING
Device
24LCS61
24LCS62
Array
Size
Voltage
Range
1K bits 2.5V-5.5V
2K bits 2.5V-5.5V
Software
Write
Protection
Entire Array
Lower Half
FEATURES
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
• Software addressability allows up to 255 devices
on the same bus
• 2-wire serial interface bus, I2C compatible
• Automatic bus arbitration
• Wakes up to control code 0110
• General purpose output pin can be used to
enable other circuitry
• 100 kHz and 400 kHz compatibility
• Page-write buffer for up to 16 bytes
• 10 ms max write cycle time for byte or page write
• 10,000,000 erase/write cycles guaranteed
• 8-pin PDIP, SOIC or TSSOP packages
• Temperature ranges supported:
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24LCS61/62 is a 1K/2K
bit Serial EEPROM developed for applications that
require many devices on the same bus but do not have
the I/O pins required to address each one individually.
These devices contain an 8 bit address register that is
set upon power-up and allows the connection of up to
255 devices on the same bus. When the process of
assigning ID values to each device is in progress, the
device will automatically handle bus arbitration if more
than one device is operating on the bus. In addition, an
external open drain output pin is available that can be
used to enable other circuitry associated with each
individual system. Low current design permits opera-
tion with typical standby and active currents of only
10 µA and 1 mA respectively. The device has a page-
write capability for up to 16 bytes of data. The device is
available in the standard 8-pin PDIP, SOIC (150 mil),
and TSSOP packages.
PACKAGE TYPES
PDIP
NC 1
NC
EDS
2
3
Vss 4
8 Vcc
7 NC
6 SCL
5 SDA
SOIC
NC
NC
EDS
Vss
1
2
3
4
TSSOP
NC
NC
EDS
VSS
1
2
3
4
8
VCC
7 NC
6 SCL
5 SDA
8 Vcc
7 NC
6 SCL
5 SDA
BLOCK DIAGRAM
EDS
HV Generator
I/O
Control
Logic
SDA SCL
Vcc
Vss
Memory
Control
Logic
XDEC
EEPROM
Array
ID Register
Serial Number
YDEC
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
© 1997 Microchip Technology Inc.
Preliminary
DS21226A-page 1

1 page




24LC61-SN pdf
24LCS61/62
3.5 Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24LCS61/62 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-2: ACKNOWLEDGE TIMING
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 3-2).
Acknowledge
Bit
SCL 1 2 3 4 5 6 7 8 9 1 2 3
SDA
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
© 1997 Microchip Technology Inc.
Preliminary
DS21226A-page 5

5 Page





24LC61-SN arduino
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command and then sending the Device ID byte for
that particular device. If the device is still busy with the
write cycle, then no ACK will be returned after the
Device ID byte. If no ACK is returned, then the start bit,
control byte and ID byte must be re-sent. If the cycle is
complete, then the device will return the ACK and the
master can then proceed with the next command. See
Figure 7-1 for flow diagram.
24LCS61/62
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control byte and
Device ID byte
Did Device
Acknowledge
Device ID
(ACK = 0)?
YES
Next
Operation
NO
© 1997 Microchip Technology Inc.
Preliminary
DS21226A-page 11

11 Page







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