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PDF 24LC52-IST Data sheet ( Hoja de datos )

Número de pieza 24LC52-IST
Descripción 2K2.5VI2CSerialEEPROMwithSoftwareWriteProtect
Fabricantes MicrochipTechnology 
Logotipo MicrochipTechnology Logotipo



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No Preview Available ! 24LC52-IST Hoja de datos, Descripción, Manual

24LCS52
2K 2.5V I2CSerial EEPROM with Software Write Protect
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
- 5 µA standby current typical at 3.0V
• Organized as a single block of 256 bytes (256 x 8)
• Software write protection for lower 128 bytes
• Hardware write protection for entire array
• 2-wire serial interface bus, I2Ccompatible
• 100kHz (2.5V) and 400kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 3.5 ms typical write cycle time for page-write
• 10,000,000 erase/write cycles guaranteed
• ESD protection >4,000V
• Data retention > 200 years
• 8-pin DIP, SOIC or TSSOP packages
• Available for extended temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24LCS52 is a 2K bit
Electrically Erasable PROM capable of operation
across a broad voltage range (2.5V to 5.5V). This
device has a software write protect feature for the lower
half of the array, as well as an external pin that can be
used to write protect the entire array. The software write
protect feature is enabled by sending the device a spe-
cial command, and once this feature has been enabled,
it cannot be reversed. In addition to the software pro-
tect feature, there is a WP pin that can be used to write
protect the entire array, regardless of whether the soft-
ware write protect register has been written or not. This
allows the system designer to protect none, half or all of
the array, depending on the application. The device is
organized as a single block of 256 x 8-bit memory with
a 2-wire serial interface. Low voltage design permits
operation down to 2.5 volts with typical standby and
active currents of only 5 µA and 1 mA respectively. The
device has a page-write capability for up to 16 bytes of
data. The device is available in the standard 8-pin DIP,
8-pin SOIC and TSSOP packages.
PACKAGE TYPES
PDIP/SOIC
A0 1
A1 2
A2 3
Vss 4
8 Vcc
7 WP
6 SCL
5 SDA
TSSOP
A0 1
A1 2
A2 3
Vss 4
8 Vcc
7 WP
6 SCL
5 SDA
BLOCK DIAGRAM
A0 A1 A2
WP
I/O
Control
Logic
Memory
Control
Logic
XDEC
SDA SCL
Vcc
Vss
HV Generator
Software write
protected area
(00h-7Fh)
Standard
Array
Write Protect
Circuitry
YDEC
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21166B-page 1

1 page




24LC52-IST pdf
24LCS52
The eighth bit of slave address determines if the master
device wants to read or write to the 24LCS52 (Figure 3-
2). When set to a one a read operation is selected and
when set to a zero a write operation is selected.
Operation
Read
Write
Set Write Protect
Register
Control
Code
1010
1010
0110
Chip
Select
A2 A1 A0
A2 A1 A0
A2 A1 A0
R/W
1
0
0
FIGURE 3-2:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W A
1 0 1 0 A2 A1 A0
OR
0 1 1 0 A2 A1 A0
4.0 WRITE OPERATIONS
4.1 Byte Write
Following the start signal from the master, the device
code(4 bits), the chip select bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24LCS52. After receiving
another acknowledge signal from the 24LCS52 the
master device will transmit the data word to be written
into the addressed memory location. The 24LCS52
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24LCS52 will not generate acknowl-
edge signals (Figure 4-1). If an attempt is made to write
to the array when the software or hardware write pro-
tection has been enabled, the device will acknowledge
the command but no data will be written. The write
cycle time must be observed even if the write protection
is enabled.
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LCS52 in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 15 additional data
bytes to the 24LCS52 which are temporarily stored in
the on-chip page buffer and will be written into the
memory after the master has transmitted a stop condi-
tion. After the receipt of each word, the four lower order
address pointer bits are internally incremented by one.
The higher order four bits of the word address remains
constant. If the master should transmit more than 16
bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2). If an attempt is
made to write to the array when the hardware write pro-
tection has been enabled, the device will acknowledge
the command but no data will be written. The write
cycle time must be observed even if the write protection
is enabled.
FIGURE 4-1:
BUS ACTIVITY
MASTER
SDA LINE
BYTE WRITE
S
T
A
R
CONTROL
BYTE
T
S
WORD
ADDRESS
BUS ACTIVITY
A
C
K
FIGURE 4-2:
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
PAGE WRITE
S
T
A CONTROL
R BYTE
T
S
WORD
ADDRESS (n)
AA
CC
KK
DATA n
A
C
K
A
C
K
DATA
S
T
O
P
P
A
C
K
DATA n + 15
S
T
O
P
P
AA
CC
KK
© 1996 Microchip Technology Inc.
Preliminary
DS21166B-page 5

5 Page





24LC52-IST arduino
24LCS52
24LCS52 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
24LCS52 —
/P
Package:
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body)
ST = TSSOP, 8-lead
Temperature
Range:
Blank = 0˚C to +70˚C
I = –40˚C to +85˚C
Device:
24LCS52 2K I2C Serial EEPROM
24LCS52T 2K I2C Serial EEPROM (Tape and Reel)
© 1996 Microchip Technology Inc.
Preliminary
DS21166B-page 11

11 Page







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