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PDF UPD8670 Data sheet ( Hoja de datos )

Número de pieza UPD8670
Descripción 7400 PIXELS CCD LINEAR IMAGE SENSOR
Fabricantes NEC 
Logotipo NEC Logotipo



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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD8670
7400 PIXELS CCD LINEAR IMAGE SENSOR
The µ PD8670 is a hi gh se nsitive a nd h igh-speed CCD ( Charge Co upled Device) li near image s ensor which c hanges
optical images to electrical signal.
The µ PD8670 is a 2-output type CCD sens or wit h 2 ro ws of high-spee d charge tr ansfer register, whi ch tr ansfers th e
photo signal electrons of 7400 pixels separately in odd and even pixels. And it has reset feed-through level clamp circuits
and voltage amplifiers. Therefore, it is suitable for 600 dpi/A3 high-speed digital copiers, multi-function products and so on.
FEATURES
Valid photocell : 7400 pixels
Photocell pitch : 4.7 µ m
Photocell size : 4.7 × 4.7 µ m2
Resolution
: 24 dot/mm (600 dpi) A3 (297 × 420 mm) size (shorter side)
Data rate
: 44 MHz MAX. (22 MHz/1 output)
Output type
: 2 outputs in-phase operation, and out of phase also supported
High sensitivity : 17.0 V/lxs TYP. (Light source: Daylight color fluorescent lamp)
Peak response wavelength : 550 nm (green)
Low image lag : 1 % MAX.
Drive clock level : CMOS output under +5 V operation
Power supply
On-chip circuits
:
: +12 V
: Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
µ PD8670CY
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16749EJ1V0DS00 (1st edition)
Date Published July 2003 NS CP (K)
Printed in Japan
http://www.Datasheet4U.com
2003

1 page




UPD8670 pdf
µ PD8670
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Output drain voltage
Shift register clock voltage
Last stage shift register clock voltage
Reset gate clock voltage
Transfer gate clock voltage
Reset feed-through level clamp clock voltage
Operating ambient temperatureNote
Storage temperature
Symbol
VOD
Vφ 1, Vφ 2
Vφ 2L
Vφ R
Vφ TG
Vφ CP
TA
Tstg
Note Use at the condition without dew condensation.
Ratings
0.3 to +14.0
0.3 to +8.0
0.3 to +8.0
0.3 to +8.0
0.3 to +8.0
0.3 to +8.0
0 to +60
40 to +70
Unit
V
V
V
V
V
V
°C
°C
Caution Product quality ma y suff er if the absolute maxim um rating is exceeded e ven momentaril y f or an y
parameter. That is, the ab solute maxim um ratings are rated v alues at whic h th e pr oduct is on the
verge of suff ering p hysical dama ge, an d theref ore the pr oduct m ust be used under cond itions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter Symbol
Output drain voltage
Shift register clock high level
Shift register clock low level
Last stage shift register clock high level
Last stage shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high level
Transfer gate clock low level
Shift register clock amplitude
Last stage shift register clock amplitude
Reset gate clock amplitude
Reset feed-through level clamp clock amplitude
Transfer gate clock amplitude
Data rate
Conditions
VOD
Vφ 1H, Vφ 2H
Vφ 1L, Vφ 2L
Vφ 2LH
Vφ 2LL
Vφ RH
Vφ RL
Vφ CPH
Vφ CPL
Vφ TGH
Vφ TGL
Vφ 1_pp,
f < 10 MHz/ch
Vφ 2_pp f
10 MHz/ch
Vφ 2L_pp
Vφ R_pp
Vφ CP_pp
Vφ TG_pp
2fφ R
MIN.
TYP.
11.4 12.0 12.6
4.5 5.0 5.5
0.3 0
4.5 5.0 5.5
0.3 0
4.5 5.0 5.5
0.3 0
4.5 5.0 5.5
0.3 0
4.5 5.0 5.5
0.3 0
4.0 5.0
4.5 5.0
4.5 5.0
4.5 5.0
4.5 5.0
4.5 5.0
12
MAX.
+0.5
+0.5
+0.5
+0.5
+0.5
5.8
5.8
5.8
5.8
5.8
5.8
44
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
MHz
Data Sheet S16749EJ1V0DS
5

5 Page





UPD8670 arduino
TIMING CHART 4 (Line clamp mode, In phase operation)
φ TG
φ 11, φ 12
φ 21, φ 22
φ 2L1, φ 2L2
φ R1, φ R2
φ CP1, φ CP2
VOUT1
VOUT2
Note
Dummy cell
(32 pixels)
Optical black
(96 pixels)
Invalid photocell
(6 pixels)
Valid photocells
(7400 pixels)
Invalid photocell
(6 pixels)
Note Set the φ R1, φ R2, φ CP1 and φ CP2 to low level during this period.

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