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PDF 24LC21A-P Data sheet ( Hoja de datos )
| Número de pieza | 24LC21A-P | |
| Descripción | 1K2.5VDualModeI2CSerialEEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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24LC21A
1K 2.5V Dual Mode I2C™ Serial EEPROM
FEATURES
• Single supply with operation down to 2.5V
• Completely implements DDC1™/DDC2™
interface for monitor identification, including recov-
ery to DDC1
• Pin and function compatible with 24LC21
• Low power CMOS technology
- 1 mA typical active current
- 10 µA standby current typical at 5.5V
• 2-wire serial interface bus, I2C™ compatible
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to eight bytes
• 10,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• ESD Protection > 4000V
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24LC21A is a 128 x 8-
bit dual-mode Electrically Erasable PROM. This device
is designed for use in applications requiring storage
and serial transmission of configuration and control
information. Two modes of operation have been imple-
mented: Transmit-Only Mode and Bi-directional Mode.
Upon power-up, the device will be in the Transmit-Only
Mode, sending a serial bit stream of the memory array
from 00h to 7Fh, clocked by the VCLK pin. A valid high
to low transition on the SCL pin will cause the device to
enter the transition mode, and look for a valid control
byte on the I2C bus. If it detects a valid control byte from
the master, it will switch into Bi-directional Mode, with
byte selectable read/write capability of the memory
array using SCL. If no control byte is received, the
device will revert to the Transmit-Only Mode after it
receives 128 consecutive VCLK pulses while the SCL
pin is idle. The 24LC21A is available in a standard 8-pin
PDIP and SOIC package in both commercial and
industrial temperature ranges.
PACKAGE TYPES
PDIP
NC 1
NC 2
NC 3
VSS 4
SOIC
8 VCC
7 VCLK
6 SCL
5 SDA
NC 1
NC 2
NC 3
VSS 4
BLOCK DIAGRAM
8 VCC
7 VCLK
6 SCL
5 SDA
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
SDA SCL
VCLK
VCC
VSS
EEPROM
ARRAY
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
DDC is a trademark of the Video Electronics Standards Association.
I2C is a trademark of Philips Corporation.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21160B-page 1
1 page  
3.0 BI-DIRECTIONAL MODE
Before the 24LC21A can be switched into the Bi-direc-
tional Mode (Figure 3-1), it must enter the transition
mode, which is done by applying a valid high to low
transition on the Bi-directional Mode Clock (SCL). As
soon it enters the transition mode, it looks for a control
byte 1010 000X on the I2C™ bus, and starts to count
pulses on VCLK. Any high to low transition on the SCL
line will reset the count. If it sees a pulse count of 128
on VCLK while the SCL line is idle, it will revert back to
the Transmit-Only Mode, and transmit its contents start-
ing with the most significant bit in address 00h. How-
ever, if it detects the control byte on the I2C™ bus,
(Figure 3-2) it will switch to the in the Bi-directional
Mode. Once the device has made the transition to the
Bi-directional mode, the only way to switch the device
back to the Transmit-Only Mode is to remove power
from the device. The mode transition process is shown
in detail in Figure 3-3.
24LC21A
Once the device has switched into the Bi-directional
Mode, the VCLK input is disregarded, with the excep-
tion that a logic high level is required to enable write
capability. This mode supports a two-wire Bi-directional
data transmission protocol (I2C™). In this protocol, a
device that sends data on the bus is defined to be the
transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be con-
trolled by a master device that generates the Bi-direc-
tional Mode Clock (SCL), controls access to the bus
and generates the START and STOP conditions, while
the 24LC21A acts as the slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated. In the Bi-
directional mode, the 24LC21A only responds to
commands for device 1010 000X.
FIGURE 3-1: MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE
MODE
Transmit
Only
SCL
Bi-directional
TVHZ
SDA
VCLK count =
VCLK
1 234
Recovery to Transmit-Only Mode
(MSB of data in 00h)
Bit8
127 128
FIGURE 3-2: SUCCESSFUL MODE TRANSITION TO BI-DIRECTIONAL MODE
Transmit
Only Mode
MODE
SCL
Bi-directional
Transition Mode with possibility to return to Transmit-Only Mode permanently
SDA
VCLK count =
VCLK
1
2
S 1 0 1 0 0 0 0 0 ACK
n0
n < 128
© 1996 Microchip Technology Inc.
Preliminary
DS21160B-page 5
5 Page 
24LC21A
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1 Current Address Read
The 24LC21A contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24LC21A
issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC21A
discontinues transmission (Figure 7-1).
FIGURE 7-1: CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
SDA LINE
S
T
A CONTROL
R
T
BYTE
S1 0 1 0 0 0 0 1
BUS ACTIVITY
A
C
K
DATA n
S
T
O
P
P
N
O
A
C
K
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC21A as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LC21A will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC21A
discontinues transmission (Figure 7-2).
7.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LC21A transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24LC21A to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC21A contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
7.4 Noise Protection
The 24LC21A employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SDA, SCL and VCLK inputs have Schmitt trigger
and filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
FIGURE 7-2: RANDOM READ
BUS ACTIVITY
MASTER
S
T
A CONTROL
R BYTE
T
WORD
ADDRESS (n)
S
T
A
R
T
CONTROL
BYTE
SDA LINE
BUS ACTIVITY
S1 01 00 00 0
A
C
K
S1010 0001
AA
CC
KK
DATA n
S
T
O
P
P
N
O
A
C
K
© 1996 Microchip Technology Inc.
Preliminary
DS21160B-page 11
11 Page | ||
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| PDF Descargar | [ Datasheet 24LC21A-P.PDF ] | |
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