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PDF ISL6353 Data sheet ( Hoja de datos )

Número de pieza ISL6353
Descripción Multiphase PWM Regulator
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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Multiphase PWM Regulator for VR12 DDR Memory
Systems
ISL6353
The ISL6353 is a three-phase PWM buck regulator controller for
VR12 DDR memory applications. The multi-phase implementation
results in better system performance, superior thermal
management, lower component cost and smaller PCB area.
The ISL6353 has two integrated power MOSFET drivers for
implementing a cost effective and space saving power
management solution.
The PWM modulator of theISL6353 is based on Intersil’s Robust
Ripple Regulator™ (R3) technology. Compared with the traditional
multi-phase buck regulator, the R3 modulator commands variable
PWM switching frequency during load transients,achieving faster
transientresponse.R3 also naturally goes into pulse frequency
modulation operation in light load conditions to achieve higher light
load efficiency.
The ISL6353 is designedto be completely compliant with VR12
specifications. The ISL6353has a serial VID (SVID) bus
communicating with the CPU. The output can be programmed for
1-, 2- or 3-phase inet rleaved operation.The output voltage and
power state can also be controlled independent of the serial VID
bus.
The ISL6353 has several other key features. It supports DCR
current sensing with a single NTC thermistor for DCR
temperature compensation or accurate resistor current sensing.
It also has remote voltage sense, adjustable switching frequency,
current monitor, OC/OV protection and power-good. Temperature
monitor and thermal alert is available too.
Features
• VR12 Serial Communications Bus
• Precision Voltage Regulation
- 5mV Steps with VID Fast/Slow Slew Rates
• Supports Two Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Programmable 1, 2 or 3-Phase Operation
• Adaptive Body Diode Conduction Time Reduction
• Superior Noise Immunity and Transient Response
• Pin Programmable Output Voltage and Power State Mode
• Output Current Monitor and Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Programmable Switching Frequency
• Resistor Programmable VBOOT, Power State Operation, SVID
Address Setting, IMAX
• Excellent Dynamic Current Balance Between Phases
• OCP/WOC, OVP, OT Alert, PGOOD
• Small Footprint 40 Ld 5x5 TQFN Package
• Pb-Free (RoHS Compliant)
Applications
•D DR Memory
COMP
200mV/DIV
VDDQ = 1.5V
50mV/DIV
PHASE1/2/3
5V/DIV
26A STEP LOAD
1V/DIV
20µs/DIV
FIGURE 1. FAST TRANSIENT RESPONSE
95
94 1.5V PS1 2ph CCM
1.5V PS0
93
92 1.5V PS2 1ph DE
91
1.35VPS0
90
89 1.35V PS1 2ph CCM
88
1.35VPS2 1ph DE
87
86
85
0 10 20 30 40 50 60 70
LOAD (A)
FIGURE 2. ISL6353EVAL1Z EFFICIENCY vs LOAD
80
FN6897.0
September 15, 2011
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
http://www.Datasheet4U.com

1 page




ISL6353 pdf
ISL6353
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
17 RTN Output voltage sense return pin. Connect to the ground at desired remote sensing location.
18, 19
ISUMN and ISUMP Inverting and non-inverting input of the transconductance amplifier for current monitoring and OCP.
20 VDD 5V bias power.
21 VIN Input supply voltage, used for input supply feed-forward compensation.
22
PROG1
The program pin for the voltage regulator IMAX setting. Refer to Table 6.
23
BOOT1
Connect an MLCC capacitor across the BOOT1 and the PH1 pins. The boot capacitor is charged through an internal
switch connected from the VDDP pin to the BOOT1 pin.
24 UG1 Output of the Phase 1 high-side MOSFET gate driver. Connect the UG1 pin to the gate of the Phase 1 high-side
MOSFET.
25 PH1 Current return path for the Phase 1 high-side MOSFET gate driver. Connect the PH1 pin to the node consisting of
the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 1.
26 GND This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the
controller or to the exposed pad on the back of the IC using a low impedance path.
27 LG1 Output of the Phase 1 low-side MOSFET gate driver. Connect the LG1 pin to the gate of the Phase 1 low-side
MOSFET.
28
PWM3
PWM output for Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable Phase 3 and allow other
phases to operate.
29
VDDP
Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1µF using an
MLCC capacitor to the ground plane close to the IC.
30 LG2 Output of the Phase 2 low-side MOSFET gate driver. Connect the LG2 pin to the gate of the Phase 2 low-side
MOSFET.
31 GND This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the
controller or to the exposed pad on the back of the IC using a low impedance path.
32 PH2 Current return path for the Phase 2 high-side MOSFET gate driver. Connect the PH2 pin to the node consisting of
the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 2.
33 UG2 Output of the Phase 2 high-side MOSFET gate driver. Connect the UG2 pin to the gate of the Phase 2 high-side
MOSFET.
34
BOOT2
Connect an MLCC capacitor across the BOOT2 and the PH2 pins. The boot capacitor is charged through an internal
switch connected from the VDDP pin to the BOOT2 pin.
35
PROG2
The program pin for the voltage regulator VBOOT voltage, droop enable/disable and the number of active phases
for PS1 mode.
36 PSI This pin can be used to set the power state of the controller with external logic signals. By connecting this pin to
ground, the controller will refer only to the power state indicated by the serial communication bus register. If the
pin is connected to a high impedance, the controller will enter the PS1 state. If the pin is connected to a logic high,
the controller will enter the PS2 state.
37
VSET2
This pin is a logic input that can be used in conjunction with VSET1 to program the output voltage of the regulator
with external logic signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to
the VID setting indicated by the serial communication bus register.
38
VSET1
This pin is a logic input that can be used in conjunction with VSET2 to program the output voltage of the regulator
with external signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to the
VID setting indicated by the serial communication bus register.
39 OVP An inverter output, latched high for an overvoltage event. It is reset by POR.
40
ADDR
This pin sets the address offset register, range from 0 to 13 (0h to Dh).
- GND (Bottom Pad) Electrical ground of the IC. Unless otherwise stated, all signals are referenced to the GND pin. Connect this ground
pad to the ground plane through a low impedance path. Recommend use of at least 5 vias to connect to ground
planes in PCB internal layers.
5 September 15, 2011
FN6897.0

5 Page





ISL6353 arduino
ISL6353
Gate Driver Timing Diagram
PWM
UGATE
tLGFUGR
tRU
tFU
1V
LGATE
tFL
1V
tUGFLGR
tRL
Theory of Operation
Multiphase R3 Modulator
VW MASTER CLOCK CIRCUIT
MASTER
MASTER COMP
CLOCK Vcrm
CLOCK
Phase
Sequencer
gmVo
Crm
Clock1
Clock2
Clock3
VW
Vcrs1
Crs1
VW
Vcrs2
Crs2
VW
Vcrs3
Crs3
SLAVE CI RCUIT 1
Clock1 S PWM1 Phase1
Q
R
L1
IL1
gm
SLAVE CI RCUIT 2
Clock2 S PWM2 Phase2
Q
R
L2
IL2
gm
SLAVE CIRCUIT 3
Clock3
S PWM3 Phase3
Q
R
L3
IL3
gm
Vo
Co
VW
Vcrm
COMP
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
PWM2
CLOCK3
PWM3
VW
HYSTERETIC
WINDOW
Vcrs2 Vcrs3
Vcrs1
FIGURE 4. R3 MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
FIGURE 3. R3 MODULATOR CIRCUIT
11 September 15, 2011
FN6897.0

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