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PDF 24LC21 Data sheet ( Hoja de datos )
| Número de pieza | 24LC21 | |
| Descripción | 1K2.5VDualModeI2CSerialEEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 24LC21 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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Not recommended for new designs –
Please use 24LCS21A.
24LC21
1K 2.5V Dual Mode I2C™ Serial EEPROM
Features:
• Single supply with operation down to 2.5V
• Completely implements DDC1™/DDC2™ interface
for monitor identification
• Low-power CMOS technology:
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
• 2-wire serial interface bus, I2C™ compatible
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Factory programming (QTP) available
• 1,000,000 erase/write cycles ensured
• Data retention > 200 years
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
Commercial (C):
Industrial (I):
0°C to +70°C
-40°C to +85°C
Description:
The Microchip Technology Inc. 24LC21 is a 128 x 8 bit
Electrically Erasable PROM. This device is designed
for use in applications requiring storage and serial
transmission of configuration and control information.
Two modes of operation have been implemented:
Transmit-only mode and Bidirectional mode. Upon
power-up, the device will be in the Transmit-only mode,
sending a serial bit stream of the entire memory array
contents, clocked by the VCLK pin. A valid high-to-low
transition on the SCL pin will cause the device to enter
the Bidirectional mode, with byte selectable read/write
capability of the memory array. The 24LC21 is available
in a standard 8-pin PDIP and SOIC package, in both
commercial and industrial temperature ranges.
Package Types
PDIP
NC 1
NC 2
NC 3
VSS 4
SOIC
NC 1
NC 2
NC 3
VSS
4
8 VCC
7 VCLK
6 SCL
5 SDA
8 VCC
7 VCLK
5 SCL
5 SDA
Block Diagram
VCLK
I/O
Control
Logic
Memory
Control
Logic
XDEC
SDA SCL
VCC
VSS
HV Generator
EEPROM
Array
Page Latches
YDEC
Sense Amp
R/W Control
I2C is a trademark of Philips Corporation.
DDC is a trademark of the Video Electronics Standards Association.
2004 Microchip Technology Inc.
DS21095J-page 1
1 page  
24LC21
3.0 BIDIRECTIONAL MODE
The 24LC21 can be switched into the Bidirectional
mode (see Figure 3-1) by applying a valid high-to-low
transition on the Bidirectional mode clock (SCL). When
the device has been switched into the Bidirectional
mode, the VCLK input is disregarded, with the exception
that a logic high level is required to enable write capa-
bility. This mode supports a two wire bidirectional data
transmission protocol. In this protocol, a device that
sends data on the bus is defined to be the transmitter,
and a device that receives data from the bus is defined
to be the receiver. The bus must be controlled by a
master device that generates the Bidirectional mode
clock (SCL), controls access to the bus and generates
the Start and Stop conditions, while the 24LC21 acts as
the slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
3.1 Bidirectional Mode Bus
Characteristics
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (see Figure 3-2).
3.1.1 BUS NOT BUSY (A)
Both data and clock lines remain high.
3.1.2 START DATA TRANSFER (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.3 STOP DATA TRANSFER (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 3-1:
SCL
MODE TRANSITION
Transmit-only mode
Bidirectional mode
TVHZ
SDA
VCLK
FIGURE 3-2:
(A)
SCL
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B) (D)
(D)
(C) (A)
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
2004 Microchip Technology Inc.
DS21095J-page 5
5 Page 
24LC21
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1 Current Address Read
The 24LC21 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 24LC21
issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a Stop condition and the 24LC21
discontinues transmission (Figure 7-1).
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC21 as part of a write operation. After the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a ‘1’. The 24LC21 will then issue
an acknowledge and transmits the eight bit data word.
The master will not acknowledge the transfer but does
generate a Stop condition and the 24LC21
discontinues transmission (Figure 7-2).
FIGURE 7-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
R
T
Control
Byte
SDA LINE
S
BUS ACTIVITY
7.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LC21 transmits the
first data byte, the master issues an acknowledge as
opposed to a Stop condition in a random read. This
directs the 24LC21 to transmit the next sequentially
addressed 8-bit word (see Figure 7-3).
To provide sequential reads the 24LC21 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
7.4 Noise Protection
The 24LC21 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
Data (n)
A
C
K
S
T
O
P
P
N
O
A
C
K
2004 Microchip Technology Inc.
DS21095J-page 11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet 24LC21.PDF ] | |
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