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PDF 24LC16B Data sheet ( Hoja de datos )
| Número de pieza | 24LC16B | |
| Descripción | EEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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1. 24LC16B pdf datasheet  Hay una vista previa y un enlace de descarga de 24LC16B (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
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24LC16B
16K I2C Serial EEPROM
Extended (-55°C to +125°C) Operating Temperatures
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
24LC16B 2.5V-5.5V 400 kHz
Temp.
Ranges
M
Features
• Single Supply with Operation down to 2.5V
• Low-Power CMOS Technology:
- Active current 1 mA, typical
- Standby current, 1 µA, typical
• 2-Wire Serial Interface, I2C Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms Maximum
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• RoHS Compliant
• Temperature Ranges:
- Extended (M): -55°C to +125°C
Description
The Microchip Technology Inc. 24LC16B is a 16 Kbit
Electrically Erasable PROM. The device is organized
as eight blocks of 256 x 8-bit memory with a 2-wire
serial interface. Low-voltage design permits operation
down to 2.5V with standby and active currents of only
1 µA and 1 mA, respectively. The 24LC16B also has a
page write capability for up to 16 bytes of data. The
24LC16B is available in the standard 8-pin SOIC and
5-lead SOT-23 packages.
Package Types
SOIC
SOT-23
A0 1
A1 2
A2 3
VSS 4
8 VCC SCL 1
7 WP VSS 2
6 SCL SDA 3
5 SDA
5 WP
4 VCC
Note: Pins A0, A1 and A2 are not used by the
24LC16B (no internal connections).
Block Diagram
WP
HV
Generator
I/O
Control
Logic
I/O SCL
SDA
VCC
VSS
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
YDEC
Sense Amp.
R/W Control
2009-2016 Microchip Technology Inc.
DS20002213B-page 1
1 page  
24LC16B
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
A0
A1
A2
VSS
SDA
SCL
WP
VCC
PIN FUNCTION TABLE
8-pin SOIC 5-pin SOT-23
1—
2—
3—
42
53
61
75
84
Description
Not Connected
Not Connected
Not Connected
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+2.5V to +5.5V Power Supply
2.1 Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an
open-drain terminal, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.2 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
2.3 Write-Protect (WP)
The WP pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to VCC, write operations are inhibited. The entire
memory will be write-protected. Read operations are
not affected.
2.4 A0, A1, A2
The A0, A1 and A2 pins are not used by the 24LC16B.
They may be left floating or tied to either VSS or VCC.
2009-2016 Microchip Technology Inc.
DS20002213B-page 5
5 Page 
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24LC16B contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address ‘n’, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 24LC16B
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24LC16B
discontinues transmission (Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24LC16B as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘1’. The
24LC16B will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24LC16B will discontinue transmission (Figure 8-2).
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read, except that once the 24LC16B transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24LC16B to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24LC16B contains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
24LC16B
8.4 Noise Protection
The 24LC16B employs a VCC threshold detector circuit
which disables the internal erase/write logic if the Vcc
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
2009-2016 Microchip Technology Inc.
DS20002213B-page 11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 24LC16B.PDF ] | |
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