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PDF ICS810251I Data sheet ( Hoja de datos )

Número de pieza ICS810251I
Descripción VCXO and Synchronous Ethernet Jitter Attenuator
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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VCXO and Synchronous Ethernet
Jitter Attenuator
ICS810251I
DATA SHEET
General Description
The ICS810251I is a high performance, low jitter/low phase noise
VCXO. The ICS810251i uses a low frequency and low cost pullable
crystal to achieve jitter attenuation for synchronous Ethernet
applications. The ICS810251I can take an input of either 25MHz or
125MHz and produce a single LVCMOS output of 25MHz.
The device is packaged in a small 16 lead TSSOP package and is
ideal for use on space constrained boards typically encountered in
most synchronous ethernet applications.
Applications
Synchronous Ethernet v0.39a
End equipment compliant with Std IEEE 802.039a
Features
One single-ended output (LVCMOS or LVTTL levels),
output Impedance: 15
Phase jitter attenuation by the VCXO-PLL using a 25MHz pullable
external crystal (XTAL)
Input frequencies: 25MHz or 125MHz
Output frequency: 25MHz
PLL loop bandwidth adjustable by external components
25MHz or 125MHz auto input frequency detect
Full 3.3V or 2.5V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
(External loop
filter inputs.)
LF1 LF0
25MHz
OE
CLK_IN
(25MHz or 125MHz
input frequency auto
detect)
Pre-
divider
(÷1 or ÷5)
PFD CP VCXO
VCXO-PLL
1
0
Q
25MHz
Pin Assignment
PLL_SEL
GND
Reserved
Q
VDDO
OE
VDDA
V DD
1
2
3
4
5
6
7
8
16 CLK_IN
15 V DD
14 LF1
13 LF0
12 GND
11 XTAL_IN
10 XTAL_OUT
9 GND
ICS810251I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
ICS810251AGI REVISION B OCTOBER 5, 2012
1
©2012 Integrated Device Technology, Inc.
http://www.Datasheet4U.com

1 page




ICS810251I pdf
ICS810251I Data Sheet
VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR
Table 4B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
fREF
fVCO
fOUT
tJIT(CC)
tjit
tJIT(PER)
tR / tF
odc
odc
Input Reference Frequency
VCXO-PLL Frequency
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
RMS Phase Jitter (Random);
NOTE 2
Period jitter
Output Rise/Fall Time
Output Duty Cycle; NOTE 3
Output Duty Cycle; NOTE 4
fOUT = 25MHz, Integration Range:
1kHz – 1MHz
20% to 80%
700
48
44
Typical
25
125
25
25
0.24
Maximum
35
10
2200
52
56
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized using a 616Hz bandwidth filter.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: Specified with the VCXO-PLL free running high.
NOTE 4: Specified with the VCXO-PLL locked.
ICS810251AGI REVISION B OCTOBER 5, 2012
5
©2012 Integrated Device Technology, Inc.

5 Page





ICS810251I arduino
ICS810251I Data Sheet
VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS810251I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS810251I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)MAX = VDD_MAX * (IDD + IDDA + IDDO) = 3.465V *(40mA + 7mA + 5mA) = 180.18mW
• Output Impedance ROUT Power Dissipation due to Loading 50to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50+ ROUT)] = 3.465V / [2 * (50+ 15)] = 26.7mA
• Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 15* (26.7mA)2 = 10.7mW per output
Dynamic Power Dissipation at 25MHz
Power (25MHz) = CPD * Frequency * (VDD)2 = 8pF * 25MHz * (3.465V)2 = 2.4mW per output
Total Power Dissipation
Total Power
= Power (core)MAX + Power (ROUT) + Power (25MHz)
= 180.18mW + 10.7mW + 2.4mW
= 193.28mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 92.4°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.193W *92.4°C/W = 102.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 5. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
JA by Velocity
Meters per Second
01
Multi-Layer PCB, JEDEC Standard Test Boards
92.4°C/W
88.0°C/W
2.5
85.9°C/W
ICS810251AGI REVISION B OCTOBER 5, 2012
11
©2012 Integrated Device Technology, Inc.

11 Page







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