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PDF 24LC04B Data sheet ( Hoja de datos )

Número de pieza 24LC04B
Descripción 4K/8K2.5VI2CSerialEEPROMs
Fabricantes MicrochipTechnology 
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24AA04/24LC04B
4K I2CSerial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
24AA04
1.7-5.5
400 kHz(1)
24LC04B 2.5-5.5
400 kHz
Note 1: 100 kHz for VCC <2.5V.
Temp.
Ranges
I
I, E
Features:
• Single Supply with Operation down to 1.7V for
24AA04 Devices, 2.5V for 24LC04B Devices
• Low-Power CMOS Technology:
- Read current 1 mA, typical
- Standby current 1 μA, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Schmitt Trigger inputs for Noise Suppression
• Output Slope Control to eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN, MSOP and 5-lead SOT-23 or 4-lead
Chip Scale
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Package Types
PDIP/MSOP/SOIC/TSSOP
SOT-23-5
Description:
The Microchip Technology Inc. 24AA04/24LC04B
(24XX04*) is a 4 Kbit Electrically Erasable PROM. The
device is organized as two blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and active currents of only 1 μA and 1 mA,
respectively. The 24XX04 also has a page write
capability for up to 16 bytes of data. The 24XX04 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 DFN, 2x3 TDFN, and MSOP
packages and is also available in the 5-lead SOT-23, or
4-lead Chip Scale package.
Block Diagram
HV
WP Generator
I/O
Control
Logic
I/O
SCL
SDA
VCC
VSS
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
YDEC
Sense Amp.
R/W Control
DFN/TDFN
CS (Chip Scale)2
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
SCL 1
Vss
SDA
2
3
5 WP
4 Vcc
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
VCC 1
SCL 3
2 VSS
4 SDA
(Top Down View,
Balls Not Visible)
Note 1: Pins A0, A1 and A2 are not used by the 24XX04. (No internal connections).
2: Available in I-temp, “AA” only.
* 24XX04 is used in this document as a generic part number for the 24LC04/24LC04B devices.
© 2009 Microchip Technology Inc.
DS21708K-page 1

1 page




24LC04B pdf
24AA04/24LC04B
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name
A0
A1
A2
VSS
SDA
SCL
WP
VCC
PDIP
1
2
3
4
5
6
7
8
SOIC TSSOP
11
22
33
44
55
66
77
88
DFN
1
2
3
4
5
6
7
8
TDFN
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
SOT23
2
3
1
5
4
CS Description
— Not Connected
— Not Connected
— Not Connected
2 Ground
4 Serial Address/Data I/O
3 Serial Clock
— Write-Protect Input
1 +1.7V to 5.5V Power Supply
2.1 Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.2 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
2.3 Write-Protect (WP)
The WP pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-1FF).
If tied to VCC, write operations are inhibited. The entire
memory will be write-protected. Read operations are
not affected.
The Chip Scale package does not support the write-
protect feature.
2.4 A0, A1, A2
The A0, A1 and A2 pins are not used by the 24XX04.
They may be left floating or tied to either VSS or VCC.
© 2009 Microchip Technology Inc.
DS21708K-page 5

5 Page





24LC04B arduino
24AA04/24LC04B
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX04 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W bit set to ‘1’, the 24XX04 issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer, but does generate a Stop
condition and the 24XX04 discontinues transmission
(Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX04 as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘1’. The
24XX04 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX04, will discontinue transmission (Figure 8-2).
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read, except that once the 24XX04 transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX04 to transmit the next sequentially-
addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24XX04 contains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
8.4 Noise Protection
The 24XX04 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
FIGURE 8-1:
CURRENT ADDRESS READ
S
Bus Activity T Control
Master
A
R
Byte
T
Data (n)
S
T
O
P
SDA Line
Bus Activity
x = “don’t care”
S 1 0 1 0 x x B0 1
Block
Select
Bits
A
C
K
P
N
o
A
C
K
© 2009 Microchip Technology Inc.
DS21708K-page 11

11 Page







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