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PDF 24FC65-ISM Data sheet ( Hoja de datos )

Número de pieza 24FC65-ISM
Descripción 64K5.0V1MHzI2CSmartSerialEEPROM
Fabricantes MicrochipTechnology 
Logotipo MicrochipTechnology Logotipo



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24FC65
64K 5.0V 1 MHz I2CSmart SerialEEPROM
FEATURES
• Voltage operating range: 4.5V to 5.5V
- Maximum write current 3 mA at 5.5V
- Maximum read current 150 µA at 5.5V
- Standby current 1 µA typical
• 1 MHz SE2.bus two wire protocol
• Up to eight devices may be connected to the
same bus for up to 512K bits total memory
• Programmable block security options
• Programmable endurance options
• Schmitt trigger inputs for noise suppression
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Endurance:
- 10,000,000 E/W cycles guaranteed for a 4K
block
- 1,000,000 E/W cycles guaranteed for a 60K
block
• Variable page size up to 64 bytes
• 8 byte x 8 line input cache (64 bytes)
for fast write loads
• <3 ms typical write cycle time, byte or page
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24FC65 is a “smart”
8K 8x 8 Serial Electrically Erasable PROM (EEPROM)
with a high-speed 1MHz SE2.bus whose protocol is
functionally equivalent to the industry-standard I2C bus.
This device has been developed for advanced applica-
tions such as personal communications, and provides
the systems designer with flexibility through the use of
many new user-programmable features. The 24FC65
offers a relocatable 4K-bit block of ultra-high-endurance
memory for data that changes frequently. The remain-
der of the array, or 60K bits, is rated at 1,000,000
ERASE/WRITE (E/W) cycles guaranteed. The 24FC65
features an input cache for fast write loads with a
capacity of eight pages, or 64 bytes. This device also
features programmable security options for E/W pro-
PACKAGE TYPES
PDIP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 NC
6 SCL
5 SDA
SOIC
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 NC
6 SCL
5 SDA
BLOCK DIAGRAM
A0..A2
I/O
CONTROL
LOGIC
I/O
SCL
SDA
MEMORY
CONTROL
LOGIC
XDEC
Vcc
Vss
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
CACHE
YDEC
SENSE AMP
R/W CONTROL
tection of critical data and/or code of up to fifteen 4K
blocks. Functional address lines allow the connection of
up to eight 24FC65's on the same bus for up to 512K bits
contiguous EEPROM memory. The 24FC65 is available
in the standard 8-pin plastic DIP and 8-pin surface
mount SOIC package.
I2C is a trademark of Philips Corporation.
Smart Serial is a trademark of Microchip Technology Inc.
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS21125B-page 1

1 page




24FC65-ISM pdf
3.6 Device Addressing
A control byte is the first byte received following the
START from the master device. The control byte consists
of a four bit control code, for the 24FC65 this is set as
1010 binary for read and write operations. The next three
bits of the control byte are the device select bits (A2, A1,
A0). They are used by the master device to select which
of the eight devices are to be accessed. These bits are
in effect the three most significant bits of the word
address. The last bit of the control byte (R/W) defines the
operation to be performed. When set to a one a read
operation is selected, when set to a zero a write opera-
tion is selected. The next two bytes received define the
address of the first data byte (Figure 4-1). Because only
A12..A0 are used, the upper three address bits must be
zeros. The most significant bit of the most significant byte
is transferred first. Following the START, the 24FC65
monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving a 1010 code and
appropriate device select bits, the slave device (24FC65)
outputs an acknowledge signal on the SDA line.
Depending upon the state of the R/W bit, the 24FC65 will
select a read or write operation.
Operation
Control
Code
Device Select
R/W
Read
Write
1010
1010
Device Address
Device Address
1
0
FIGURE 3-2: CONTROL BYTE
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W A
1 0 1 0 A2 A1 A0
X = Don’t care
24FC65
4.0 WRITE OPERATION
4.1 Byte Write
Following the START from the master, the control code
(four bits), the device select (three bits), and the R/W bit
which is a logic low is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver (24FC65) that a byte with a word address will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmitted
by the master is the high-order byte of the word address
and will be written into the address pointer of the
24FC65. The next byte is the least significant address
byte. After receiving another acknowledge signal from
the 24FC65 the master device will transmit the data word
to be written into the addressed memory location. The
24FC65 acknowledges again and the master generates
a STOP. This initiates the internal write cycle, and during
this time the 24FC65 will not generate acknowledge sig-
nals (Figure 4-1).
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24FC65 in the same way as
in a byte write. But instead of generating a STOP the
master transmits up to eight pages of eight data bytes
each (64 bytes total) which are temporarily stored in the
on-chip page cache of the 24FC65. They will be written
from the cache into the EEPROM array after the master
has transmitted a STOP. After the receipt of each word,
the six lower order address pointer bits are internally
incremented by one. The higher order seven bits of the
word address remain constant. If the master should
transmit more than eight bytes prior to generating the
STOP (writing across a page boundary), the address
counter (lower three bits) will roll over and the pointer will
be incremented to point to the next line in the cache. This
can continue to occur up to eight times or until the cache
is full, at which time a STOP should be generated by the
master. If a STOP is not received, the cache pointer will
roll over to the first line (byte 0) of the cache, and any
further data received will overwrite previously captured
data. The STOP can be sent at any time during the
transfer. As with the byte write operation, once the STOP
is received an internal write cycle will begin. The 64 byte
cache will continue to capture data until a STOP occurs
or the operation is aborted (Figure 4-2).
FIGURE 4-1: BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
S
T CONTROL
A BYTE
R
T
BUS ACTIVITY
WORD
ADDRESS (1)
WORD
ADDRESS (0)
000
A
C
K
A
C
K
A
C
K
DATA
S
T
O
P
A
C
K
© 1996 Microchip Technology Inc.
DS21125B-page 5

5 Page





24FC65-ISM arduino
24FC65
8.0 PIN DESCRIPTIONS
8.1 A0, A1, A2 Chip Address Inputs
The A0..A2 inputs are used by the 24FC65 for multiple
device operation and conform to the two-wire bus
standard. The levels applied to these pins define the
address block occupied by the device in the address
map. A particular device is selected by transmitting the
corresponding bits (A2, A1, A0) in the control byte
(Figure 3-2 and Figure 8-1).
8.2 SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to VCC (typical 1KΩ, must consider total bus
capacitance and maximum rise/fall times).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOPs.
8.3 SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
FIGURE 8-1: CONTROL SEQUENCE BIT ASSIGNMENTS
CONTROL
BYTE
ADDRESS
BYTE 1
ADDRESS
BYTE 0
CONFIGURATION
BYTE
1
0
1
0
A
2
AAR
1 0W
Slave Device
Address Select
Bits
S
0
0
A AA
12 11 10
A
9
A
8
A
7
••
A
0
R
X
X
B
3
B
2
B
1
B
0
S/HE
Block
Count
Security Read
Acknowledge
No
S
atr
Acknowledges from Device
from Master
ACK
Data from Device
Data from Device
S
ot
t Rp
1
0
1
0
A
2
AA
10
A
0
C
K
1
XXXX
XX
A
XC X
K
XXXX
XX
A
X
C
K
1
1 XXX
XX
A
XC
K
1
1
1
1
B
3
B
2
B
1
B
0
A
C
K
1
1
1
1
N NN N
3 21 0
S/HE
Starting Block
Number of
Security Write
Number
Blocks to
Protect
S
atr
Acknowledges from Device
S
ot
t Rp
1
01
0
A
2
A
1
A
0
A
0
C
K
1
X
X
B
3
B
2
B
1
B
0
A
XC X
K
XXXX
XX
A
X
C
K
1
0
X
X
N
3
N
2
N
1
N
0
A
C
K
Starting Block
S/HE
Number of
Number
Blocks to
Protect
High Endurance Block Read
No
S
atr
Acknowledges from Device
ACK
Data from Device
S
ot
t Rp
1
01
0
A
2
A
1
A
0
A
0
C
K
1
XXXX
XX
A
XC X
K
XXXX
XX
A
X
C
K
0
1 XXX
XX
A
XC
K
1
1
1
1
B BB
3 21
B
0
A
C
K
S/HE
High Endurance
Block Number
High Endurance Block Write
S
atr
t
Acknowledges from Device
R
S
ot
p
1
01
0
A
2
A
1
A
0
A
0
C
K
1
X
X
B
3
B
2
B
1
B
0
A
XC X
K
XXXX
XX
A
X
C
K
00
XX
0
0
0
A
0C
K
S/HE
High Endurance
Block Number
© 1996 Microchip Technology Inc.
DS21125B-page 11

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