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PDF 24C16 Data sheet ( Hoja de datos )
| Número de pieza | 24C16 | |
| Descripción | 2-Wire Serial EEPROM | |
| Fabricantes | ATMELCorporation | |
| Logotipo |  |
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 1. 16KBit, EEPROM Memory, 8 Pin  Hay una vista previa y un enlace de descarga de 24C16 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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Features
• Medium-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 100 kHz (2.7V) and 400 kHz (5V) Compatibility
• Write Protect Pin for Hardware Data Protection
• 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
• Partial Page Writes are Allowed
• Self-timed Write Cycle (5 ms max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP and 8-lead JEDEC SOIC Packages
Description
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec-
trically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP and 8-lead
JEDEC SOIC packages and is accessed via a two-wire serial interface. In addition,
the entire family is available in 5.0V (4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions.
Table 1. Pin Configuration
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
8-lead PDIP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-lead SOIC
Two-wire
Automotive
Serial EEPROM
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
AT24C01A
AT24C02
AT24C04
AT24C08(1)
AT24C16(2)
Note: 1. This device is not recom-
mended for new designs.
Please refer to AT24C08A.
2. This device is not recom-
mended for new designs.
Please refer to AT24C16A.
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
3256F–SEEPR–10/04
1
1 page  
AT24C01A/02/04/08/16
Table 5. AC Characteristics
Applicable over recommended operating range from TA = −40°C to +125°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
AT24C01A/02/04/08,
2.7V
AT24C16, 2.7V
AT24C01A/02/04/08/16,
5.0V
Symbol
fSCL
tLOW
tHIGH
tI
tAA
tBUF
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(2)
Clock Low to Data Out Valid
Time the bus must be free before
a new transmission can start(3)
Min
1.2
0.6
0.1
1.2
Max Min Max
400(1)
400
1.2
0.6
50 50
0.9 0.1 0.9
1.2
Min
1.2
0.6
0.1
1.2
Max Units
400 kHz
µs
µs
50 ns
0.9 µs
µs
tHD.STA
Start Hold Time
0.6 0.6 0.6
µs
tSU.STA
Start Set-up Time
0.6 0.6 0.6
µs
tHD.DAT
Data In Hold Time
0
00
µs
tSU.DAT
tR
tF
Data In Set-up Time
Inputs Rise Time(3)
Inputs Fall Time(3)
100 100 100
300 300
300 300
ns
300 ns
300 ns
tSU.STO
Stop Set-up Time
0.6 0.6 0.6
µs
tDH Data Out Hold Time
50
50 50
ns
tWR Write Cycle Time
55
5 ms
Endurance 5.0V, 25°C
1M
1M 1M
Write
Cycles
Notes:
1. The AT24C01A/02/04/08 bearing the process letter “D” on the package (the mark is located in the lower right corner on the
topside of the package), guarantees 400 kHz (2.5V, 2.7V).
2. This parameter is characterized and is not 100% tested (TA = 25°C).
3. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
3256F–SEEPR–10/04
5
5 Page 
Figure 11. Random Read
(* = DON’T CARE bit for 1K)
Figure 12. Sequential Read
AT24C01A/02/04/08/16
3256F–SEEPR–10/04
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet 24C16.PDF ] | |
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