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PDF 24C1024 Data sheet ( Hoja de datos )
| Número de pieza | 24C1024 | |
| Descripción | 2-wire Serial EEPROM 1M | |
| Fabricantes | ATMELCorporation | |
| Logotipo |  |
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Features
• Low-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• Internally Organized 131,072 x 8
• 2-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 400 kHz (2.7V) and 1 MHz (5V) Clock Rate
• Write Protect Pin for Hardware and Software Data Protection
• 256-byte Page Write Mode (Partial Page Writes Allowed)
• Random and Sequential Read Modes
• Self-timed Write Cycle (5 ms Typical)
• High Reliability
– Endurance: 100,000 Write Cycles/Page
www.DataShee–t4UD.acotamRetention: 40 Years
• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead LAP and 8-ball dBGATM Packages
2-wire Serial
EEPROM
1M (131,072 x 8)
Description
The AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-
mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The
device’s cascadable feature allows up to 2 devices to share a common 2-wire bus. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operation are essential. The devices are available in space-
saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP) and 8-ball dBGA
packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions.
AT24C1024
Pin Configurations
Pin Name
A1
SDA
SCL
WP
NC
Function
Address Input
Serial Data
Serial Clock Input
Write Protect
No Connect
8-lead SOIC
NC
A1
NC
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-lead PDIP
NC
A1
NC
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-lead Leadless Array
VCC 8
WP 7
SCL 6
SDA 5
1 NC
2 A1
3 NC
4 GND
Bottom View
8-ball dBGA
VCC
WP
SCL
SDA
8
7
6
5
1 NC
2 A1
3 NC
4 GND
Bottom View
Rev. 1471H–SEEPR–03/03
1
1 page  
AT24C1024
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +2.7V to +5.5V, CL = 100 pF (unless
otherwise noted). Test conditions are listed in Note 2.
Symbol
Parameter
Test Conditions
Min
Max Units
fSCL Clock Frequency, SCL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
tLOW Clock Pulse Width Low
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
tHIGH
Clock Pulse Width High
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
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tAA
Clock Low to Data Out Valid
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
tBUF
Time the bus must be free before a new
transmission can start(1)
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
tHD.STA
Start Hold Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
tSU.STA
Start Setup Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
tHD.DAT
Data In Hold Time
tSU.DAT
tR
Data In Setup Time
Inputs Rise Time(1)
tF Inputs Fall Time(1)
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
tSU.STO
Stop Setup Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
tDH Data Out Hold Time
tWR
Endurance(1)
Write Cycle Time
5.0V, 25°C, Page Mode
Notes:
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.7V, 5V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤50 ns
Input and output timing reference voltages: 0.5 VCC
0.4
1.3
0.4
0.6
0.05
0.05
0.5
1.3
0.25
0.6
0.25
0.6
0
100
0.25
0.6
50
100K
1000
400
0.55
0.9
0.3
100
300
10
kHz
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write Cycles
1471H–SEEPR–03/03
5
5 Page 
Figure 1. Device Address
0
Figure 2. Byte Write
www.DataSheet4U.com
MOST
SIGNIFICANT
LEAST
SIGNIFICANT
P0
Figure 3. Page Write
MOST
SIGNIFICANT
P0
LEAST
SIGNIFICANT
Figure 4. Current Address Read
AT24C1024
1471H–SEEPR–03/03
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet 24C1024.PDF ] | |
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