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PDF 24C08 Data sheet ( Hoja de datos )
| Número de pieza | 24C08 | |
| Descripción | 8K/16K 5.0V I2C Serial EEPROMs | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 24C08 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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24C08B/16B
8K/16K 5.0V I2C™ Serial EEPROMs
FEATURES
• Single supply with operation from 4.5-5.5V
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
• Organized as 4 or 8 blocks of 256 bytes
(4 x 256 x 8) or (8 x 256 x 8)
• 2-wire serial interface bus, I2C™ compatible
• Schmitt trigger, filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• 100 kHz compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• ESD protection > 4,000V
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead or 14-lead SOIC packages
• Available for extended temperature range
- Automotive (E):
-40˚C to +125˚C
DESCRIPTION
The Microchip Technology Inc. 24C08B/16B is an 8K or
16K bit Electrically Erasable PROM intended for use in
extended/automotive temperature ranges. The device
is organized as four or eight blocks of 256 x 8-bit mem-
ory with a 2-wire serial interface. The 24C08B/16B also
has a page-write capability for up to 16 bytes of data.
The 24C08B/16B is available in the standard 8-pin DIP
and both 8-lead and 14-lead surface mount SOIC pack-
ages.
I2C is a trademark of Philips Corporation.
PACKAGE TYPES
PDIP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
8-lead
SOIC
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
14-lead
SOIC
NC 1
A0 2
A1 3
NC 4
A2 5
VSS 6
NC 7
14 NC
13 VCC
12 WP
11 NC
10 SCL
9 SDA
8 NC
BLOCK DIAGRAM
WP
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
SDA SCL
EEPROM
ARRAY
PAGE LATCHES
YDEC
VCC SENSE AMP
VSS R/W CONTROL
© 1996 Microchip Technology Inc.
DS21081D-page 1
This document was created with FrameMaker 4 0 4
1 page  
24C08B/16B
3.6 Device Addressing
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24C08B/16B this
is set as 1010 binary for read and write operations. The
next three bits of the control byte are the block select
bits (B2, B1, B0). They are used by the master device
to select which of the eight 256 word blocks of memory
are to be accessed. These bits are in effect the three
most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24C08B/16B monitors
the SDA bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24C08B/16B will select a
read or write operation.
Operation
Read
Write
Control
Code
1010
1010
Block Select
Block Address
Block Address
R/W
1
0
FIGURE 3-2:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W A
1 0 1 0 B2 B1 B0
4.0 WRITE OPERATION
4.1 Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24C08B/16B. After receiving
another acknowledge signal from the 24C08B/16B the
master device will transmit the data word to be written
into the addressed memory location. The 24C08B/16B
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24C08B/16B will not generate
acknowledge signals (Figure 4-1).
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24C08B/16B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to 16 data bytes to
the 24C08B/16B which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
FIGURE 4-1:
BUS ACTIVITY
MASTER
BYTE WRITE
S
T
A
R
CONTROL
BYTE
T
WORD
ADDRESS
SDA LINE
S
BUS ACTIVITY
A
C
K
FIGURE 4-2:
BUS ACTIVITY
MASTER
SDA LINE
PAGE WRITE
S
T
A CONTROL
R BYTE
T
S
BUS ACTIVITY
WORD
ADDRESS (n)
AA
CC
KK
DATA n
DATA
S
T
O
P
P
AA
CC
KK
DATA n + 1
DATA n + 15
S
T
O
P
P
AAA
CCC
KKK
© 1996 Microchip Technology Inc.
DS21081D-page 5
5 Page 
24C08B/16B
24C08B/16B Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
24C08B/16B – E /P
Package:
Temperature
Range:
P = Plastic DIP (300 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
SN = Plastic SOIC (150 mil Body), 8-lead
E = -40°C to +125°C
Device:
24C08B
24C08BT
24C16B
24C16BT
8K I2C Serial EEPROM
8K I2C Serial EEPROM (Tape and Reel)
16K I2C Serial EEPROM
16K I2C Serial EEPROM (Tape and Reel)
© 1996 Microchip Technology Inc.
DS21081D-page 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 24C08.PDF ] | |
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