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PDF 24C04A-ESM Data sheet ( Hoja de datos )

Número de pieza 24C04A-ESM
Descripción 1K/2K/4K 5.0V I2C Serial EEPROMs
Fabricantes MicrochipTechnology 
Logotipo MicrochipTechnology Logotipo



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24C01A/02A/04A
1K/2K/4K 5.0V I2CSerial EEPROMs
FEATURES
• Low power CMOS technology
• Hardware write protect
• Two wire serial interface bus, I2Ccompatible
• 5.0V only operation
• Self-timed write cycle (including auto-erase)
• Page-write buffer
• 1ms write cycle time for single byte
• 1,000,000 Erase/Write cycles guaranteed
• Data retention >200 years
• 8-pin DIP/SOIC packages
• Available for extended temperature ranges
- Commercial (C):
- Industrial (I):
- Automotive (E):
0˚C to +70˚C
-40˚C to +85˚C
-40˚C to +125˚C
DESCRIPTION
The Microchip Technology Inc. 24C01A/02A/04A is a
1K/2K/4K bit Electrically Erasable PROM. The device
is organized as shown, with a standard two wire serial
interface. Advanced CMOS technology allows a signif-
icant reduction in power over NMOS serial devices. A
special feature in the 24C02A and 24C04A provides
hardware write protection for the upper half of the block.
The 24C01A and 24C02A have a page write capability
of two bytes and the 24C04A has a page length of eight
bytes. Up to eight 24C01A or 24C02A devices and up
to four 24C04A devices may be connected to the same
two wire bus.
This device offers fast (1ms) byte write and
extended (-40°C to 125°C) temperature operation. It
is recommended that all other applications use
Microchip’s 24LCXXB.
Organization
Write Protect
Page Write
Buffer
24C01A
128 x 8
None
2 Bytes
24C02A
258 x 8
080-0FF
2 Bytes
24C04A
2 x 256 x 8
100-1FF
8 Bytes
PACKAGE TYPES
DIP A0 1
A1 2
A2 3
VSS 4
8-lead
SOIC A0
A1
A2
VSS
1
2
3
4
14-lead
SOIC
NC
A0
A1
NC
1
2
3
4
A2 5
VSS 6
NC 7
* “TEST” pin in 24C01A
BLOCK DIAGRAM
Vcc
Vss
SDA
Data
Buffer
(FIFO)
Data Reg.
Slave Addr.
SCL
Control
Logic
I2C is a trademark of Philips Corporation.
A0 A1 A2 WP
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
8 VCC
7 WP*
6 SCL
5 SDA
8 VCC
7 WP*
6 SCL
5 SDA
14 NC
13 VCC
12 WP
11 NC
10 SCL
9 SDA
8 NC
Vpp R/W Amp
AP
do
di
rn
et
se
A0 to
A7
sr
Memory
Array
Increment
A8
DS11183D-page 1

1 page




24C04A-ESM pdf
4.0 SLAVE ADDRESS
The chip address inputs A0, A1 and A2 of each 24C01A/
02A/04A must be externally connected to either VCC or
ground (VSS), assigning to each 24C01A/02A/04A a
unique address. A0 is not used on the 24C04A and
must be connected to either VCC or VSS. Up to eight
24C01A or 24C02A devices and up to four 24C04A
devices may be connected to the bus. Chip selection is
then accomplished through software by setting the bits
A0, A1 and A2 of the slave address to the corresponding
hard-wired logic levels of the selected 24C01A/02A/04A.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C01A/02A/04A, followed by the
chip address bits A0, A1 and A2. In the 24C04A, the
seventh bit of that byte (A0) is used to select the upper
block (addresses 100—1FF) or the lower block
(addresses 000—0FF) of the array.
The eighth bit of slave address determines if the master
device wants to read or write to the 24C01A/02A/04A
(Figure 4-1).
The 24C01A/02A/04A monitors the bus for its corre-
sponding slave address all the time. It generates an
acknowledge bit if the slave address was true and it is
not in a programming mode.
FIGURE 4-1: SLAVE ADDRESS
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W A
1 0 1 0 A2 A1 A0
5.0 BYTE PROGRAM MODE
In this mode, the master sends addresses and one data
byte to the 24C01A/02A/04A.
Following the START signal from the master, the device
code (4-bits), the slave address (3-bits), and the R/W
bit, which is logic LOW, are placed onto the bus by the
master. This indicates to the addressed 24C01A/02A/
04A that a byte with a word address will follow after it
has generated an acknowledge bit. Therefore the next
byte transmitted by the master is the word address and
will be written into the address pointer of the 24C01A/
02A/04A. After receiving the acknowledge of the
24C01A/02A/04A, the master device transmits the data
word to be written into the addressed memory location.
The 24C01A/02A/04A acknowledges again and the
master generates a STOP condition. This initiates the
internal programming cycle of the 24C01A/02A/04A
(Figure 6-1).
24C01A/02A/04A
6.0 PAGE PROGRAM MODE
To program the 24C01A/02A/04A, the master sends
addresses and data to the 24C01A/02A/04A which is
the slave (Figure 6-1 and Figure 6-2). This is done by
supplying a START condition followed by the 4-bit
device code, the 3-bit slave address, and the R/W bit
which is defined as a logic LOW for a write. This indi-
cates to the addressed slave that a word address will
follow so the slave outputs the acknowledge pulse to
the master during the ninth clock pulse. When the word
address is received by the 24C01A/02A/04A, it places
it in the lower 8 bits of the address pointer defining
which memory location is to be written. (The A0 bit
transmitted with the slave address is the ninth bit of the
address pointer for the 24C04A). The 24C01A/02A/04A
will generate an acknowledge after every 8-bits
received and store them consecutively in a RAM buffer
until a STOP condition is detected. This STOP condi-
tion initiates the internal programming cycle. The RAM
buffer is 2 bytes for the 24C01A/02A and 8 bytes for the
24C04A. If more than 2 bytes are transmitted by the
master to the 24C01A/02A, the device will not acknowl-
edge the data transfer and the sequence will be
aborted. If more than 8 bytes are transmitted by the
master to the 24C04A, it will roll over and overwrite the
data beginning with the first received byte. This does
not affect erase/write cycles of the EEPROM array and
is accomplished as a result of only allowing the address
registers bottom 3 bits to increment while the upper 5
bits remain unchanged.
If the master generates a STOP condition after trans-
mitting the first data word (Point ‘P’ on Figure 6-1), byte
programming mode is entered.
The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received data bytes in the page
buffer will be written in a serial manner.
The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 8 for
24C04A, 2 for 24C01A/02A).
© 1996 Microchip Technology Inc.
DS11183D-page 5

5 Page





24C04A-ESM arduino
24C01A/02A/04A
24C01A/02A/04A Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
24C01A/02A/04A -
/P
Package:
P = Plastic DIP
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (207 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead, 24C04A only
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
E = -40°C to +125°C
Device:
24C01A
24C01AT
24C02A
24C02AT
24C04A
24C04AT
1K I2C Serial EEPROM
1K I2C Serial EEPROM (Tape and Reel)
2K I2C Serial EEPROM
2K I2C Serial EEPROM (Tape and Reel)
4K I2C Serial EEPROM
4K I2C Serial EEPROM (Tape and Reel)
© 1996 Microchip Technology Inc.
DS11183D-page 11

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