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PDF IDT70V261L Data sheet ( Hoja de datos )

Número de pieza IDT70V261L
Descripción HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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HIGH-SPEED 3.3V
16K x 16 DUAL-PORT
Š STATIC RAM
IDT70V261S/L
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT70V261S
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V261L
Active: 300mW (typ.)
Standby: 660µW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70V261 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP, Thin Quad Plastic Flatpack
Industrial temperature range (-40°C to +85°C) is available
for selected speed
Green parts available, see ordering information
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
LBR
CER
OER
I/O8L-I/O15L
I/O0L-I/O7L
BUSYL(1,2)
A13L
A0L
I/O
Control
I/O
Control
Address
Decoder
14
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
14
SEML
INTL(2)
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
©2012 Integrated Device Technology, Inc.
M/S
1
Address
Decoder
I/O8R-I/O15R
I/O0R-I/O7R
BUSYR (1,2)
A13R
A0R
CER
OER
R/WR
SEMR
INTR(2)
3040 drw 01
SEPTEMBER 2012
DSC-3040/11
http://www.Datasheet4U.com

1 page




IDT70V261L pdf
IDT70V261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature
Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)
70V261X25
Com'l
& Ind
70V261X35
Com'l Only
70V261X55
Com'l O nly
Symbol
Parameter
Test Condition
Version
Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
ICC Dynamic Op erating
Current
(Both Ports Active)
CE = V IL, O utputs Disabled
SEM = V IH
f = fMAX(3)
COM'L
IND
S 100 170 90
L 100 140 90
S 100 200 ____
L 100 185 ____
140 90
120 90
____ ____
____ ____
140 mA
120
____ mA
____
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CER = CEL = V IH
SEMR = SEML = V IH
f = fMAX(3)
COM'L
S 14
30
12
30
12
30 mA
L 12 24 10 24 10 24
IND S 14 60 ____ ____ ____ ____ mA
L 12 50 ____ ____ ____ ____
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = V IL and CE"B" = V IH(5)
Active Po rt Outputs Disabled,
f=fMAX(3)
SEMR = SEML = V IH
COM'L S 50 95 45 87 45 87 mA
L 50 85 45 75 45 75
IND S 50 130 ____ ____ ____ ____ mA
L 50 105 ____ ____ ____ ____
ISB3 Full S tandby Current
(Both Ports -
CMOS Level Inputs)
Both P orts CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L
S 1.0
6
1.0
6
1.0
6 mA
L 0.2 3 0.2 3 0.2 3
IND S 1.0 6 mA____ ____ ____ ____
L 0.2 3 ____ ____ ____ ____
ISB4 Full S tandby Current
(One Port -
CMOS Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0. 2V(5)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
COM'L S 60 90 55 85 55 85 mA
L 60 80 55 74 55 74
IND S 60 125 ____ ____ ____ ____ mA
L 60 90 ____ ____ ____ ____
NOTES:
3040 tbl 09
1. 'X' in part number indicates power rating (S or L)
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.542

5 Page





IDT70V261L arduino
IDT70V261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Timing Waveform of Write with BUSY
tWP
R/W"A"
BUSY"B"
tWB
Industrial and Commercial Temperature
Ranges
tWH (1)
R/W"B"
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
(2)
3040 drw 12
Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
CE"B"
BUSY"B"
tAPS (2)
tBAC
tBDC
3040 drw 13
Waveform of BUSY Arbitration Cycle Controlled by
Address Match Timing(1)
ADDR"A"
ADDR"B"
BUSY"B"
tAPS (2)
ADDRESS "N"
MATCHING ADDRESS "N"
tBAA
tBDA
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
3040 drw 14
61.412

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