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PDF VT1708S Data sheet ( Hoja de datos )
| Número de pieza | VT1708S | |
| Descripción | High Definition Audio Codec | |
| Fabricantes | VIA | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de VT1708S (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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Data Sheet
VT1708S
High Definition Audio Codec
January 6, 2009
(Released under Creative Commons License)
Preliminary Revision 1.0
1 page  
Data Sheet
VT1708S High Definition Audio Codec
2
2 Overview
The VIA VT1708S is a quality High Definition Audio Codec that conforms to Intel High Definition Audio
Specification Rev.1.0 and with performance exceeds Microsoft Windows Logo Program (WLP)
Requirements. It supports 100-dB DAC SNR and 90-dB ADC SNR. VT1708S features four 24-bit stereo
digital-to-analog converter (DAC) and two 24-bit analog-to-digital converter (ADC) channels, supporting
audio sampling rates up to 192 kHz. VT1708S is capable of supporting various audio output stream
formats.
The two independent 16-, 20-, 24-bit S/PDIF TX Output channels of VT1708S support sampling rates of
48 kHz, 96 kHz, 192 kHz, 44.1 kHz, and 88.2 kHz. The second S/PDIF TX Out is dedicated for digital audio
output to a HDMI transmitter. The Analog Microphone Input supports software-selectable gain boost of
10-dB, 20-dB, and 30-dB. VT1708S features high-pass-filter (HPF) in analog-to-digital converter (ADC)
path for removing DC offset signals.
The built-in Jack-detect Circuit allows to sense if an audio device is plugged in. The Front Panel Jack
Re-tasking function facilitates flexible configurations. In addition, VT1708S provides two GPIO (General
Purpose Input and Output) pins for customized applications. VT1708S is suitable for high performance
and power efficient audio applications. VT1708S is available in the 7 mm × 7 mm 48-Pin LQFP lead-free
and RoHS compliant package
5 Page 
Data Sheet
VT1708S High Definition Audio Codec
The following figure shows the timing diagram of BITCLK, SYNC, SDO and SDI.
8
Figure 4 – Bit Timing Diagram
Figure 5 – SYNC and SDO Timing Relative to BITCLK
Figure 5 shows that both SYNC and SDO may be toggled with respect to either edge of BITCLK. In
particular, bit cell n+1 is driven by the controller on SDO with respect to clock edge #2, and is sampled
by the codec with respect to the subsequent clock edge, #3, and so forth.
Figure 6 – SDI Timing Relative to BITCLK
Figure 6 shows that SID may only be toggled with respect to the rising edge of BITCLK. In particular, bit
cell n+1 is driven by the codec on SDI with respect to rising clock edge #2 and is sampled by the
controller with respect to the subsequent rising clock edge, #3, and so forth.
11 Page | ||
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