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PDF 24C02C Data sheet ( Hoja de datos )
| Número de pieza | 24C02C | |
| Descripción | 2K 5.0V I2C Serial EEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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24C02C
2K 5.0V I2C™ Serial EEPROM
Features:
• Single-supply with operation from 4.5 to 5.5V
• Low-power CMOS technology:
- Read current 1 mA, typical
- Standby current 10 μA, typical
• 2-wire serial interface, I2C compatible
• Cascadable up to eight devices
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz and 400 kHz clock compatibility
• Fast Page or Byte write time 1 ms, typical
• Self-timed erase/write cycle
• 16-byte page write buffer
• Hardware write-protect for upper half of the array
(80h-FFh)
• ESD protection >4,000V
• More than 1 million erase/write cycles
• Data retention >200 years
• Factory programming available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN and MSOP
• Pb-free and RoHS compliant
• Temperature ranges:
- Industrial (I):
- Automotive (E):
-40°C to +85°C
-40°C to +125°C
Description:
The Microchip Technology Inc. 24C02C is a 2K bit
Serial Electrically Erasable PROM with a voltage range
of 4.5V to 5.5V. The device is organized as a single
block of 256 x 8-bit memory with a 2-wire serial
interface. Low-current design permits operation with
typical standby and active currents of only 10 μA and 1
mA, respectively. The device has a page write capabil-
ity for up to 16 bytes of data and has fast write cycle
times of only 1 ms for both byte and page writes.
Functional address lines allow the connection of up to
eight 24C02C devices on the same bus for up to 16K
bits of contiguous EEPROM memory. The device is
available in the standard 8-pin PDIP, 8-pin SOIC (3.90
mm), 8-pin 2x3 DFN, 8-pin MSOP and TSSOP
packages.
Package Types
PDIP, MSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC A0
7 WP A1
6 SCL A2
5 SDA VSS
SOIC, TSSOP
1 8 VCC
2 7 WP
3 6 SCL
4 5 SDA
DFN
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
Block Diagram
A0 A1 A2
WP
I/O
Control
Logic
Memory
Control
Logic
XDEC
HV Generator
EEPROM
Array
SDA SCL
Vcc
Vss
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
I2C is a trademark of Philips Corporation.
© 2007 Microchip Technology Inc.
DS21202G-page 1
1 page  
24C02C
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All opera-
tions must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first-in first-
out fashion.
4.5 Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The 24C02C does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition (Figure 4-2).
FIGURE 4-1:
SCL (A) (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(C) (D)
(C) (A)
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL 1 2 3 4 5 6 7 8 9 1 2 3
Stop
Condition
SDA
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
© 2007 Microchip Technology Inc.
DS21202G-page 5
5 Page 
24C02C
1st Line Marking Codes
Part Number
TSSOP
MSOP
24C02C
4C2C
4C2CT
Note: T = Temperature grade (I, E)
DFN
I Temp.
2P7
E Temp.
2P8
Legend:
XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
© 2007 Microchip Technology Inc.
DS21202G-page 11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet 24C02C.PDF ] | |
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