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PDF 24C00 Data sheet ( Hoja de datos )
| Número de pieza | 24C00 | |
| Descripción | 128-Bit I2C Bus Serial EEPROM | |
| Fabricantes | MicrochipTechnology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 24C00 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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24AA00/24LC00/24C00
128-Bit I2C™ Bus Serial EEPROM
Device Selection Table
Device
VCC Range
24AA00
24LC00
24C00
1.8-5.5
2.5-5.5
4.5-5.5
Temp Range
I
I
I,E
Features:
• Single Supply with Operation down to 1.8V for
24AA00 Devices, 2.5V for 24LC00 Devices
• Low-Power CMOS Technology:
- Read current 500 A, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, Typical
• Self-Timed Erase/Write Cycle
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN and 5-lead SOT-23
• Pb-Free and RoHS Compliant
• Temperature Ranges Available:
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
Description:
The Microchip Technology Inc. 24AA00/24LC00/
24C00 (24XX00*) is a 128-bit Electrically Erasable
PROM memory organized as 16 x 8 with a 2-wire
serial interface. Low-voltage design permits operation
down to 1.8 volts for the 24AA00 version, and every
version maintains a maximum standby current of only
1 A and typical active current of only 500 A. This
device was designed for where a small amount of
EEPROM is needed for the storage of calibration
values, ID numbers or manufacturing information, etc.
The 24XX00 is available in 8-pin PDIP, 8-pin SOIC
(3.90 mm), 8-pin TSSOP, 8-pin 2x3 DFN, TDFN and
the 5-pin SOT-23 packages.
Package Types
8-PIN PDIP/SOIC
NC 1
NC 2
NC 3
Vss 4
8-PIN TSSOP
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 NC
6 SCL
5 SDA
8 VCC
7 NC
6 SCL
5 SDA
5-PIN SOT-23
SCL
VSS
SDA
1
2
3
5 VCC
4 NC
DFN/TDFN
NC 1
NC 2
NC 3
VSS 4
8 VCC
7 NC
6 SCL
5 SDA
Block Diagram
I/O
Control
Logic
Memory
Control
Logic
XDEC
HV Generator
EEPROM
Array
SDA SCL
VCC
VSS
YDEC
Sense AMP
R/W Control
*24XX00 is used in this document as a generic part number for
the 24AA00/24LC00/24C00 devices.
I2C is a trademark of Philips Corporation.
1996-2011 Microchip Technology Inc.
DS21178H-page 1
1 page  
24AA00/24LC00/24C00
3.0 FUNCTIONAL DESCRIPTION
The 24XX00 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions, while the
24XX00 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited.
1996-2011 Microchip Technology Inc.
DS21178H-page 5
5 Page 
24AA00/24LC00/24C00
FIGURE 8-2:
RANDOM READ
S
BUS ACTIVITY
MASTER
T
A
R
T
Control
Byte
Word
Address(n)
S10 10xxx0 x xxx
SDA LINE
A
C
BUS ACTIVITY
K
x = “don’t care” bit
S
T
A Control
R Byte
T
S 10 10xxx 1
AA
CC
KK
Data (n)
S
T
O
P
P
N
O
A
C
K
FIGURE 8-3:
SEQUENTIAL READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
Control
Byte
A
C
K
Data n
Data n + 1
Data n + 2
AAA
CCC
KKK
Data n + x
S
T
O
P
P
N
O
A
C
K
1996-2011 Microchip Technology Inc.
DS21178H-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 24C00.PDF ] | |
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