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PDF 24AA16 Data sheet ( Hoja de datos )

Número de pieza 24AA16
Descripción 16K 1.8V I2C Serial EEPROM
Fabricantes MicrochipTechnology 
Logotipo MicrochipTechnology Logotipo



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24AA16/24LC16B
16K I2CSerial EEPROM
Device Selection Table
Part
Number
Vcc
Range
Max. Clock
Frequency
24AA16
1.8-5.5
400 kHz(1)
24LC16B 2.5-5.5
400 kHz
Note 1: 100 kHz for VCC <2.5V
Temp.
Ranges
I
I, E
Features:
• Single supply with operation down to 1.8V
• Low-power CMOS technology:
- 1 mA active current, typical
- 1 μA standby current (max.) (I-temp)
• Organized as 8 blocks of 256 bytes (8 x 256 x 8)
• 2-wire serial interface bus, I2C™ compatible
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (2.5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 16 bytes
• Hardware write-protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP, DFN and MSOP
packages
• 5-lead SOT-23 package
• Pb-free finish available
• Available temperature ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
*24XX16 is used in this document as a generic part
number for the 24AA16/24LC16B devices.
Description:
The Microchip Technology Inc. 24AA16/24LC16B
(24XX16*) is a 16 Kbit Electrically Erasable PROM.
The device is organized as eight blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V with standby
and active currents of only 1 μA and 1 mA,
respectively. The 24XX16 also has a page write
capability for up to 16 bytes of data. The 24XX16 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 DFN and MSOP packages, and is
also available in the 5-lead SOT-23 package.
Package Types
PDIP, MSOP
SOIC, TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC A0
7 WP A1
6 SCL A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOT-23-5
DFN
SCL 1
Vss
SDA
2
3
5 WP
4 Vcc
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
Note:
Pins A0, A1 and A2 are not used by the 24XX16 (no
internal connections).
Block Diagram
WP
HV
Generator
I/O
Control
Logic
I/O SCL
SDA
VCC
VSS
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
YDEC
Sense Amp.
R/W Control
© 2005 Microchip Technology Inc.
DS21703F-page 1

1 page




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24AA16/24LC16B
2.0 FUNCTIONAL DESCRIPTION
The 24XX16 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX16 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus Not Busy (A)
Both data and clock lines remain high.
3.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically
unlimited, (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur it will replace data in a first-in first-out (FIFO)
fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The 24XX16 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX16) will leave the data line
high to enable the master to generate the Stop
condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
SCL
(B)
(D)
(D)
(C) (A)
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
© 2005 Microchip Technology Inc.
DS21703F-page 5

5 Page





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24AA16/24LC16B
8.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 8-1.
TABLE 8-1: PIN FUNCTION TABLE
Name
A0
A1
A2
VSS
SDA
SCL
WP
VCC
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
DFN
1
2
3
4
5
6
7
8
8.1 Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
8.2 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
MSOP
1
2
3
4
5
6
7
8
SOT-23
2
3
1
5
4
Description
Not Connected
Not Connected
Not Connected
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.8V to 5.5V Power Supply
8.3 Write-Protect (WP)
The WP pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 0007-FF).
If tied to VCC, write operations are inhibited. The entire
memory will be write-protected. Read operations are
not affected.
This feature allows the user to use the 24XX16 as a
serial ROM when WP is enabled (tied to VCC).
8.4 A0, A1, A2
The A0, A1 and A2 pins are not used by the 24XX16.
They may be left floating or tied to either VSS or VCC.
© 2005 Microchip Technology Inc.
DS21703F-page 11

11 Page







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