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PDF CY14B116S Data sheet ( Hoja de datos )

Número de pieza CY14B116S
Descripción 16-Mbit (2048 K x 8/1024 K x 16/512 K x 32) nvSRAM
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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PRELIMINARY
CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
16-Mbit (2048 K × 8/1024 K × 16/512 K × 32)
nvSRAM
Features
16-Mbit nonvolatile static random access memory (nvSRAM)
25-ns, 30-ns and 45-ns access times
Internally organized as 2048 K × 8 (CY14X116L),
1024 K × 16 (CY14X116N), 512 K × 32 (CY14X116S)
Hands-off automatic STORE on power-down with only a
small capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
Sleep mode operation
Low power consumption
Active current of 75 mA at 45 ns
Standby mode current of 650 A
Sleep mode current of 10 A
Operating voltages:
CY14B116X: VCC = 2.7 V to 3.6 V
CY14E116X: VCC = 4.5 V to 5.5 V
Industrial temperature: –40 C to +85 C
Packages
44-pin thin small-outline package (TSOP II)
48-pin thin small-outline package (TSOP I)
54-pin thin small-outline package (TSOP II)
165-ball fine-pitch ball grid array (FBGA) package
Restriction of hazardous substances (RoHS) compliant
Offered speeds
44-pin TSOP II: 25 ns and 45 ns
48-pin TSOP I: 30 ns and 45 ns
54-pin TSOP II: 25 ns and 45 ns
165-ball FBGA: 25 ns and 45 ns
Functional Description
The C ypress CY14X1 16L/CY14X116N/CY14X116S i s a fast
SRAM, with a no nvolatile el ement in each memory cel l. T he
memory is organized as 2048 K bytes of 8 bits each or 1024 K
words of 16 bits each o r 512 K words of 32 bit s each . T he
embedded non volatile elemen ts inco rporate Qu antumTrap
technology, prod ucing the world’s mo st reli able nonvolatile
memory. The SRAM can be read and written an infinite number
of times. The nonvolatile d ata residin g in the nonvolatile
elements do not change when data is written to the SRAM. Data
transfers from th e SRAM to the nonvolatile e lements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from th e non volatile me mory. Both th e ST ORE an d RECALL
operations are also available under software control.
Errata: The engineering samples do not meet the address hold after end of write (tHA) and static discharge voltage specifications. For information on silicon errata, see
Errata on page 33. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-67793 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 1, 2014http://www.Datasheet4U.com

1 page




CY14B116S pdf
PRELIMINARY CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
Pinouts (continued)
Figure 4. Pin Diagram: 48-Pin TSOP I (×16)
A15
A14
A13
A12
A11
A10
A9
A8
A1[96]
NC
WE
CE2
VCAP
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 - TSOP I
(x16)
Top View
(not to scale)
48 A16
47 HSB
46 VSS
45 DQ15
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39
38
DQ12
DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE
27 VSS
26 CE1
25 A0
Figure 5. Pin Diagram: 165-Ball FBGA (×16)
123456789
A
NC A6
A8
WE
BLE
CE1
NC
OE
A5
B
NC
DQ0
DQ1
A4
BHE
CE2
NC
A2
NC
C ZZ NC NC VSS A0 A7 A1 VSS NC
D
NC
DQ2
NC
VSS
VSS
VSS
VSS
VSS
NC
E
NC VCAP NC
VCC
VSS
VSS
VSS
VCC
NC
F
NC
DQ3
NC
VCC
VCC
VSS
VCC
VCC
NC
G
HSB
NC
NC
VCC
VCC
VSS
VCC
VCC
NC
H
NC
NC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
J
NC
NC
NC
VCC
VCC
VSS
VCC
VCC
NC
K NC NC DQ4 VCC VCC VSS VCC VCC NC
L
NC
DQ5
NC
VCC
VSS
VSS
VSS
VCC
NC
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
N
NC
DQ6
DQ7
VSS
A11
A10
A9
VSS NC
P NC NC NC A13 A19 NC A18 A12 NC
R NC NC A15 NC A17 NC A16 NC[6] A14
10
A3
NC
DQ15
NC
DQ13
NC
NC
NC
DQ8
NC
NC
DQ10
NC
DQ11
NC
11
NC
NC
DQ14
NC
NC
DQ12
NC
NC
NC
NC
DQ9
NC
NC
NC
NC
Note
6. Address expansion for 32-Mbit. NC pin not connected to die.
Document #: 001-67793 Rev. *G
Page 5 of 38

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CY14B116S arduino
PRELIMINARY CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
Table 1. Mode Selection
CE[10]
H
L
L
L
WE
X
H
L
H
OE
X
L
X
L
LH
L
LH
L
LH
L
BLE, BHE / BA, BB, BC, BD[11]
X
L
L
X
A15 - A0[12]
X
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Mode
Not selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
I/O
Output High Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Power
Standby
Active
Active
Active[13]
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[13]
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[13]
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[13]
Notes
10. TSOP II package is offered in single CE. TSOP I and BGA packages are offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal
logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not
permitted on any of the chip enable pins (CE for the single chip enable device; CE1 and CE2 for the dual chip enable device).
11. BLE, BHE are applicable for the ×16 configuration and BA, BB, BC, BD are applicable for the ×32 configuration only.
12. While there are 21 address lines on the CY14X116L (20 address lines on the CY14X116N and 19 address lines on the CY14X116S), only 13 address lines (A14–A2)
are used to control software modes. The remaining address lines are don’t care.
13. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile operation.
Document #: 001-67793 Rev. *G
Page 11 of 38

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