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PDF LF3311 Data sheet ( Hoja de datos )
| Número de pieza | LF3311 | |
| Descripción | Horizontal - Vertical Digital Image Filter | |
| Fabricantes | LOGIC | |
| Logotipo |  |
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DEVICES INCORPORATED
LF3311
Horizontal / Vertical Digital Image Filter
Improved Performance
FEATURES
111 MHz Data Rate
12-bit Data and Coefficients
On-board Memory for 256 Horizontal and 256 Verti-
cal Coefficient Sets
LF Interface™ Allows All 512 Coefficient Sets to be
Updated Within Vertical Blanking
Selectable 12-bit Data Output with User-Defined
Rounding and Limiting
Seven 3K x 12-bit, Programmable Two-Mode Line
Buffers
16 Horizontal Filter Taps
8 Vertical Filter Taps
Two Operating Modes: Dimensionally Sepa-
rate and Orthogonal
Supports Interleaved Data Streams
Horizontal Filter Supports Decimation up to
16:1 for Increasing Number of Filter Taps
3.3 Volt Power Supply
5 Volt Tolerant I/O
144 Lead PQFP
DESCRIPTION
The LF3311 is an improved version of the LF3310 Horizontal/Vertical Digital Image Filter capable of
operating at speeds of up to 111MHz. This improved speed will increase flexibility and performance. The
added performance will enable you to use this device in more applications. For example, four interleaved
data streams of 27MHz can now be processed within one device. The part is functionally identical to the
LF3310 with the exception that the filter data path is specified to operate faster than the LF Control Interface.
When operating the filter at speeds in excess of 90MHz, loading of coefficients via the LF Interface must
be throttled to a maximum of 90MHz by asserting the PAUSE pin as required to allow sufficient setup time
for the configuration data provided to the Figure 1 below demonstrates the switching waveforms of case 2,
while the switching characteristics are shown in Table 1.
Figure 1. Switching Waveforms: LF InterfaceTM
CLK
LDA
LDB
PAUSEA
PAUSEB
CFA 11-0
CFB 11-0
tS0
tCFH
tCFS
ADDRESS
tPS
tPWL
tPWH
tCYC
tPH
CF0
tLH
CF1
The LF3311 remains a two-dimensional digital image filter capable of filtering data at real-time video rates.
The device contains both a horizontal and a vertical filter which may be cascaded or used concurrently for
two-dimensional filtering. The input, coefficient, and output data are all 12-bits and in two’s complement
format. The horizontal filter is designed to take advantage of symmetric coefficient sets. When symmetric
coefficient sets are used, the horizontal filter can be configured as a 16-tap FIR filter. When asymmetric
coefficient sets are used, it can be configured as an 8-tap FIR filter. The vertical filter is an 8-tap FIR
filter with all required line buffers contained on-chip. The line buffers can store video lines with lengths
from 4 to 3076 pixels. Horizontal filter Interleave/Decimation Registers (I/D Registers) and the vertical filter
line buffers allow interleaved data to be fed directly into the device and filtered without separating the data
into individual data streams. The horizontal filter can handle a maximum of sixteen data sets interleaved
together. The vertical filter can handle interleaved video lines which contain 3076 or less data values. The
I/D Registers and horizontal accumulator facilitate using decimation to increase the number of filter taps
in the horizontal filter. It will support a decimation factor of up to 16:1. The device has on-chip storage
for 256 horizontal coefficient sets and 256 vertical coefficient sets. Each filter’s coefficients are loaded
independently of each other allowing one filter’s coefficients to be updated without affecting the other filter’s
coefficients. In addition, a horizontal or vertical coefficient set can be updated independently from the other
coefficient sets in the same filter.
LOGIC Devices Incorporated
Video Imaging Products
1 9/19/05 LDS.3311-Chttp://www.Datasheet4U.com
1 page  
DEVICES INCORPORATED
LF3311
Horizontal / Vertical Digital Image Filter
Improved Performance
I/D Register Data
Path Control
Functional Description
The multiplexer in the middle of the I/D Register data path controls how data is fed to the reverse data path.
The forward data path contains the I/D Registers in which data flows from left to right in the block diagram in
Figure 1. The reverse data path contains the I/D Registers in which data flows from right to left. When the
filter is configured for an even number of taps, data from the last I/D Register in the forward data path is fed
into the first I/D Register in the reverse data path (see Figure 5).
Figure 5. I/D Register Data Paths
A ALU B
A ALU B
A ALU B
A ALU B
Delay Stage N 1
Delay Stage N
A ALU B
A ALU B
COEF 7
COEF 6
COEF 7
2
COEF 6
COEF 7
2
COEF 6
Data Reversal
EVEN-TAP MODE
ODD-TAP MODE
ODD-TAP INTERLEAVE MODE
When the filter is configured for an odd number of taps, the data which will appear at the output of the last
I/D Register in the forward data path on the next clock cycle is fed into the first I/D Register in the reverse
data path. Bit 5 in Configuration Register 1 configures the filter for an even or odd number of taps.
When interleaved data is fed through the device and an even tap filter is desired, the filter should be
configured for an even number of taps (Bit 5 of CR1 set to “0”) and the I/D Register length should match
the number of data sets interleaved together. When interleaved data is to be fed through the device and
an odd tap filter is desired, the filter should be set to Odd-Tap Interleave Mode. Bit 0 of Configuration
Register 1 configures the filter for Odd-Tap Interleave Mode. When the filter is configured for Odd-Tap
Interleave Mode, data from the next to last I/D Register in the forward data path is fed into the first I/D
Register in the reverse data path.
When the filter is configured for an odd number of taps (interleaved or non-interleaved modes), the filter is
structured such that the center data value is aligned simultaneously at the A and B inputs of the last ALU in
the forward data path. In order to achieve the correct result, the user must divide the coefficient by two.
Data reversal circuitry is placed after the multiplexer which routes data from the forward data path to the
reverse data path (see Figure 6). When decimating, the data stream must be reversed in order for data to be
properly aligned at the inputs of the ALUs. When data reversal is enabled, the circuitry uses a pair of LIFOs
to reverse the order of the data sent to the reverse data path. When TXFR goes LOW, the LIFO sending
data to the reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO
receiving data from the forward data path becomes the LIFO sending data to the reverse data path. The
device must see a HIGH to LOW transition of TXFR in order to switch LIFOs. If decimating by N, TXFR
should go low once every N clock cycles. When data reversal is disabled, the circuitry functions like an
I/D Register. When feeding interleaved data through the filter, data reversal should be disabled. Bit 6 of
Configuration Register 1 enables or disables data reversal.
LOGIC Devices Incorporated
Video Imaging Products
5 9/19/05 LDS.3311-C
5 Page 
DEVICES INCORPORATED
LF3311
Horizontal / Vertical Digital Image Filter
Improved Performance
Coefficient
Banks
Configuration
and Control
Registers
Functional Description
The coefficient banks store the coefficients which feed into the multipliers in the horizontal and vertical
filters. There is a separate bank for each multiplier. Each bank can hold 256 12-bit coefficients. The banks
are loaded using an LF Interface™. There is a separate LF Interface™ for the horizontal and vertical banks.
Coefficient bank loading is discussed in the LF Interface™ section.
The Configuration Registers determine how the HV Filter operates. Tables 2 through 7 show the formats
of the six configuration registers. There are three types of control registers: round, select, and limit. There
are sixteen round registers for the horizontal filter and sixteen for the vertical filter. Each register is 32-bits
wide. HRSL3-0 and VRSL3-0 determine which horizontal and vertical round registers respectively are
used for rounding.
There are sixteen select registers for the horizontal filter and sixteen for the vertical filter. Each register is
5-bits wide. HRSL3-0 and VRSL3-0 determine which horizontal and vertical select registers respectively
are used in the select circuitry.
There are sixteen limit registers for the horizontal filter and sixteen for the vertical filter. Each register is
24-bits wide and stores both an upper and lower limit value. The lower limit is stored in bits 11-0 and the
upper limit is stored in bits 23-12. HRSL3-0 and VRSL3-0 determine which horizontal and vertical limit
registers respectively are used for limiting when limiting is enabled. Configuration and Control Register
loading is discussed in the LF Interface™ section.
Figure 8. Coefficient Bank Loading Sequence
COEFFICIENT SET 1
COEFFICIENT SET 2
COEFFICIENT SET 3
CLK
HLD/VLD
HCF/VCF11-0
ADDR1 COEF0
W1
COEF7 ADDR2 COEF0
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W2: Coefficient Set 2 written to coefficient banks during this clock cycle.
W3: Coefficient Set 3 written to coefficient banks during this clock cycle.
W2
COEF7 ADDR3 COEF0
W3
COEF7
Figure 9. Configurational/Control Register Loading Sequence
CONFIG REG
SELECT REG
ROUND REGISTER
LIMIT REGISTER
CLK
HLD/VLD
HCF/VCF11-0
W1 W2
W3 W4
ADDR1 DATA1 ADDR2 DATA1 ADDR3 DATA1 DATA2 DATA3 DATA4 ADDR4 DATA1 DATA2
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
W3: Round Register loaded with new data on this rising clock edge.
W4: Limit Register loaded with new data on this rising clock edge.
LOGIC Devices Incorporated
Video Imaging Products
11 9/19/05 LDS.3311-C
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LF3311.PDF ] | |
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