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PDF L7C108 Data sheet ( Hoja de datos )
| Número de pieza | L7C108 | |
| Descripción | 128K x 8 Static RAM | |
| Fabricantes | LOGIC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de L7C108 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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FEATURES
128K x 8 Static RAM with Chip
Select Powerdown, Output Enable
and Single or Dual Chip Selects
High Speed — to 15 ns maximum
Operational Power, -L Version
Active: 140 mA at 15 ns
Standby: 1 mA max
Data Retention at 2 V for Battery
Backup Operation
Screened to MIL-STD-883, Class B
or to SMD 5962-89598
Package Styles Available:
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xSLQ&HUDPLF/&& .
xSLQ&HUDPLF62- <
xSLQ4XDG&HUDPLF/&& .$
L7C108
L7C109
128K x 8 Static RAM
Pin Configuration
32-pin Ceramic DIP
32-pin Ceramic SOJ
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
32-pin Quad CLCC
32-pin Ceramic LCC
4 3 2 1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
5
6
7
8
9
10
11
12
13
Top
View
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 DQ8
14 15 16 17 18 19 20
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
OVERVIEW
The L7C108 and L7C109 are high-perfor-
mance, low-power CMOS static RAMs.
The storage circuitry is organized as
131,072 words by 8 bits per word. The
8 Data In and Data Out signals share I/O
pins. The L7C108 has a single active-
low Chip Enable. The L7C109 has two
&KLS (QDEOHV RQH DFWLYHORZ 7KHVH
devices are available in three speeds
with maximum access times from 15 ns
to 45 ns.
Inputs and outputs are TTL compatible.
Operation is from a single +5 V power
supply. Power consumption is 140 mA
/ 9HUVLRQ DW QV 'DWD PD\ EH
retained in inactive storage with a supply
voltage as low as 2 V.
The L7C108 and L7C109 provide asyn-
FKURQRXV XQFORFNHG RSHUDWLRQ ZLWK
matching access and cycle times. The
Chip Enables and a three-state I/O bus
with a separate Output Enable control
simplify the connection of several chips
for increased storage capacity.
Memory locations are specified on
address pins A 0 through A 16. For the
L7C108, reading from a designated
location is accomplished by present-
ing an address and driving CE 1 and OE
LOW while WE remains HIGH. For the
L7C109, CE 1 and OE must be LOW
while CE2 and WE are HIGH.The data in
the addressed memory location will then
appear on the Data Out pins within one
access time. The output pins stay in a
high-impedance state when CE1 or OE is
HIGH, or CE2 /& RU:(LV/2:
Writing to an addressed location is
accomplished when the active-low CE 1
and WE inputs are both LOW, and CE 2
/& LV+,*+$Q\RIWKHVHVLJQDOV
may be used to terminate the write oper-
ation. Data In and Data Out signals have
the same polarity.
Latchup and static discharge protection
are provided on-chip. The L7C108 and
L7C109 can withstand an injection cur-
rent of up to 200 mA on any pin without
damage.
LOGIC Devices Incorporated
www.logicdevices.com
1
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-Ghttp://www.Datasheet4U.com
1 page  
SWITCHING CHARACTERISTICS Over Operating Range
READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)
Symbol
tPD
tCDR
Parameter
2SHUDWLRQ5HFRYHU\7LPH 1RWHV
&KLS(QDEOH+LJKWR'DWD5HWHQWLRQ 1RWH
DATA RETENTION Notes 9, 10
VCC
CE
DATA RETENTION MODE
tCDR
VIH
4.5 V
L7C108
L7C109
128K x 8 Static RAM
L7C108/109
15/15-L 20/20-L 25/25-L 35/35-L 45/45-L
Min Max Min Max Min Max Min Max Min Max
15 20 25 35 45
0000 0
4.5 V
≥2V
tPD
VIH
WRITE CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)
Symbol Parameter
tAVAV Write Cycle Time
tELWH Chip Enable Low to End of Write Cycle
tAVWL Address Valid to Beginning of Write Cycle
tAVWH Address Setup to End of Write Cycle
tWHAX Address Hold After End Of Write
tWLWH Write Enable Pulse Width Low
tDVWH Data Setup to End of Write Cycle
tWHDX Data Hold to End of Write
t:+4; :ULWH(QDEOH+LJKWR2XWSXW/RZ= 1RWHV
t:/4= :ULWH(QDEOH/RZWR2XWSXW+LJK= 1RWHV
L7C108/109
15/15-L 20/20-L 25/25-L 35/35-L 45/45-L
Min Max Min Max Min Max Min Max Min Max
15 20 25 35 45
12 12 20 25 35
0 00 00
15 17 20 25 35
0 00 00
12 15 20 30 40
7 10 12 20 20
0 00 00
5 55 55
7 8 10 25 30
LOGIC Devices Incorporated
www.logicdevices.com
5
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
5 Page 
SMD Cross Reference Table
LOGIC Part #
SMD Part #
L7C109DMB45 5962-8959835MZA
L7C109DMB35 5962-8959836MZA
L7C109DMB25 5962-8959837MZA
L7C109DMB20 5962-8959838MZA
L7C109DMB15
5962-8959841MZA
L7C109YMB45 5962-8959835M7A
L7C109YMB35 5962-8959836M7A
L7C109YMB25 5962-8959837M7A
L7C109YMB20
5962-8959838M7A
L7C109YMB15
5962-8959841M7A
L7C109YMB45 5962-8959835MYA
L7C109YMB35 5962-8959836MYA
L7C109YMB25 5962-8959837MYA
L7C109YMB20
5962-8959838MYA
L7C109YMB15
5962-8959841MYA
L7C109KAMB45
5962-8959835MMA
L7C109KAMB35
5962-8959836MMA
L7C109KAMB25
5962-8959837MMA
L7C109KAMB20
5962-8959838MMA
L7C109KAMB15
5962-8959841MMA
L7C109KMB45 5962-8959835MUA
L7C109KMB35 5962-8959836MUA
L7C109KMB25 5962-8959837MUA
L7C109KMB20 5962-8959838MUA
L7C109KMB15
5962-8959841MUA
L7C108
L7C109
128K x 8 Static RAM
LOGIC Part #
SMD Part #
L7C108DMB45
5962-8959827MZA
L7C108DMB35
5962-8959828MZA
L7C108DMB25
5962-8959829MZA
L7C108DMB20
5962-8959839MZA
L7C108DMB15
5962-8959844MZA
L7C108YMB45
5962-8959827M7A
L7C108YMB35
5962-8959828M7A
L7C108YMB25
5962-8959829M7A
L7C108YMB20 5962-8959839M7A
L7C108YMB15
5962-8959844M7A
L7C108YMB45
5962-8959827MYA
L7C108YMB35
5962-8959828MYA
L7C108YMB25
5962-8959829MYA
L7C108YMB20 5962-8959839MYA
L7C108YMB15
5962-8959844MYA
LOGIC Devices Incorporated
www.logicdevices.com
11
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet L7C108.PDF ] | |
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