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PDF FSDM101 Data sheet ( Hoja de datos )
| Número de pieza | FSDM101 | |
| Descripción | Green Mode Fairchild Power Switch | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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www.fairchildsemi.com
FSDM101
Green Mode Fairchild Power Switch (FPSTM)
Features
• Internal Avalanche Rugged Sense FET
• Precision Fixed Operating Frequency (67kHz)
• Internal Start-up Switch and Soft Start
• Under Voltage Lock Out (UVLO) with Hysteresis
• Pulse by Pulse Current Limit
• Over Load Protection (OLP)
• Over Voltage Protection (OVP)
• Internal Thermal Shutdown Function (TSD)
• Secondary Side Regulation
• Auto-Restart Mode
Applications
• Charger & Adaptor for Mobile Phone, PDA & MP3
• Auxiliary Power for White Goods, PC, C-TV & Monitor
• SMPS for VCR, SVR, STB, DVD, and DVCD
• Adaptor for Camcorder
Description
The FSD M101 is an inte grated Pu lse Width Modula tor
(PWM) and Sense FET spec ially designed for high pe rfor-
mance of f-line Switc h Mode Pow er Supplies (SMPS) with
minimal exte rnal co mponents. This device is a m onolithic
high v oltage po wer sw itching reg ulator which combine s a
VDMOS Sense FET with a voltag e mode PW M co ntrol
block. The inte grated PW M co ntroller features inc lude: a
fixed oscillat or, Under V oltage Lo ck Out (UV LO) prote c-
tion, Leading Edge Blanking (LEB), optimized gate turn-on/
turn-off driver, thermal shut down protection (TSD), temper-
ature co mpensated precision current sources fo r loop c om-
pensation and fault protection circuitry. When compared to a
discrete MO SFET and controller or RCC switching con-
verter solution, the FSDM101 red uces total co mponent
count, d esign siz e, weigh t and a t the same time in creases
efficiency, productivity, and system reliability. This device is
a basic platform well suited for cost effective designs of fly-
back converters.
TYPICAL OUTPUT POWER CAPABILITY
PRODUCT
Open Frame(1)
230VAC ±15%(2)
85-265VAC
FSDM101
13W
8W
PEAK OUTPUT POWER CAPABILITY(3)
PRODUCT
Open Frame(1)
230VAC ±15%(2)
85-265VAC
FSDM101
17W
12W
Table 1. Notes: 1. Maximum practical continuous power
in an open frame design with asufficient drain pattern as
a heat sinker at 50°C ambient temperature. 2. 230 VAC or
100/115 VAC with doubler. 3. Peak output power means
the maximum power can be handled instantaneously.
Typical Circuit
AC
IN
Vstr Drain
PWM
Vfb Vcc Source
DC
OUT
Figure 1. Typical Flyback Application Using FSDM101
FPSTM is a trademark of Fairchild Semiconductor Corporation.
©2005 Fairchild Semiconductor Corporation
Rev.1.0.1
http://www.Datasheet4U.com
1 page  
FSDM101
Electrical Characteristics (Sense FET Part)
(Ta = 25°C unless otherwise specified)
Parameter
SENSE FET SECTION
Zero Gate Voltage Drain Current
Static Drain-Source on Resistance
(Note)
Forward Trans conductance (Note)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn on Delay Time
Rise Time
Turn Off Delay Time
Fall Time
Total Gate Charge
(Gate-Source + Gate-Drain)
Gate-Source Charge
Gate-Drain (Miller) Charge
Symbol
Condition
Min. Typ. Max. Unit
IDSS
VDS=Max. Rating,
VGS=0V
VDS=0.8Max. Rating,
VGS=0V, TC=125°C
-- 25
- - 200
RDS(ON) VGS=10V, ID=0.5A
- 14 19
gfs
CISS
COSS
CRSS
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
VDS=50V, ID=0.5A
VGS=0V, VDS=25V,
f=1MHz
VDD=0.5B VDSS,
ID=1.0A
(MOSFET switching time
is essentially
independent of
operating temperature)
VGS=10V, ID=1.0A,
VDS=0.5B VDSS
(MOSFET switching time
is essentially
independent of operating
temperature)
1.0
-
-1
-3
-9
-
-
-
-7
-
-
1.3
162
8-
.8
.5
19
33
42
.0
3.1
0.4
-
-
-
-
-
-
-
-
-
-
µA
µA
Ω
S
pF
ns
nC
Note:
1. Pulse test: Pulse width ≤ 300µS, duty ≤ 2%
2. S = R-1--
5
5 Page 
FSDM101
OSC
Vfb
Vfb
4
Cfb
2.5uA 400uA
R
+
-
OLP
RESET
Vth 4.5V
TSD
SQ
R
GATE
DRIVER
SQ
R
A/R
FSDM101
OLP, TSD
Protection Block
OLP
4.5V
3.8V
FPS Switching Area
Idelay (5uA) charges Cfb
IC Reset
Figure 7. Protection Block
4.1 Over Load Protection (OLP) : Overload is a load cur-
rent that exceeds a pre-set level due to an abnormal situation.
If this occurs, the protection circuit should be triggered to
protect the SMPS. It is possible that a short term load tran-
sient can occur under normal operation. If this occurs, the
system should not shut down. In order to avoid false shut-
downs, the over load protection circuit is designed to trigger
after a delay. Therefore the device can discriminate between
transient overloads and true fault conditions. The device is
pulse-by-pulse current limited and therefore, for a given
input voltage, the maximum input power is limited. If the
load tries to draw more than this, the output voltage will drop
below its set value. This reduces the opto-coupler LED cur-
rent, which in turn, will reduce the photo-transistor current.
Therefore, the 400uA current source will charge the feed-
back pin capacitor, Cfb, and the feedback voltage, Vfb, will
increase. The input to the feedback comparator is clamped at
around 3.8V. Therefore, once Vfb reaches 3.8V, the device is
switching at maximum power. At this point the 400uA cur-
rent source is blocked and the 2.5uA source continues to
charge Cfb. Once Vfb reaches 4.5V, switching stops. There-
fore the shutdown delay time is set by the time required to
charge Cfb from 3.8V to 4.5V with 2.5uA, as shown in Fig-
ure 8.
4.2 Thermal Shutdown (TSD) : The Sense FET and the
control IC are assembled in one package. This makes it easy
for the control IC to detect the temperature of the Sense FET.
When the temperature exceeds approximately 145°C, ther-
mal shutdown is activated.
t1 t2
t1<<t2, t3
t1 = -1/RC Χ ln( 1-v(t1)/R )
t2 = C Χ [v(t1+t2)-v(t1)] Χ Idelay
t3
v(t1)=3.8V
t
Figure 8. Over Load Protection Delay
5. Soft Start : The FPS has an internal soft start circuit that
increases the drain current limit together with the MOSFET
current slowly after it starts up. The soft start time is typi-
cally 15msec as shown in Figure 9. It progressively
increases during the start-up phase. The pulse width to the
power switching devices is progressively increased to estab-
lish the correct working conditions for transformers, induc-
tors, and capacitors. The voltage on the output capacitors is
progressively increased with the intention of smoothly estab-
lishing the required output voltage. Consequently it prevents
transformer saturation and stress on the secondary diodes.
Drain current [A]
0.75A
0.49A
0.46A
0.43A
0.40A
0.37A
0.34A
0.31A
2mS
7steps
Figure 9. Internal Soft Start
t
11
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet FSDM101.PDF ] | |
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