PDF 2128E Data sheet ( Hoja de datos )

Número de pieza	2128E
Descripción	In-SystemProgrammableSuperFASTHighDensityPLD
Fabricantes	LatticeSemiconductor
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No Preview Available ! ispLSI® 2128E In-System Programmable SuperFAST™ High Density PLD Features Functional Block Diagram • SUPERFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC Output Routing Pool (ORP) Output Routing Pool (ORP) — 6000 PLD Gates D7 D6 D5 D4 D3 D2 D1 D0 — 128 I/O Pins, Eight Dedicated Inputs A0 C7 — 128 Registers — High Speed Global Interconnect A1 C6 — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. A2 DQ C5 — Small Logic Block Size for Random Logic — 100% Functional/JEDEC Upward Compatible with ispLSI 2128 Devices A3 A4 Logic Array DQ DQ GLB C4 C3 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 180 MHz Maximum Operating Frequency — tpd = 5.0 ns Propagation Delay A5 A6 DQ C2 C1 — TTL Compatible Inputs and Outputs — 5V Programmable Logic Core A7 Global Routing Pool (GRP) C0 — ispJTAG™ In-System Programmable via IEEE 1149.1 B0 B1 B2 B3 B4 B5 B6 B7 (JTAG) Test Access Port — User-Selectable 3.3V or 5V I/O Supports Mixed- Output Routing Pool (ORP) Output Routing Pool (ORP) Voltage Systems 0139(9A)/2128 — PCI Compatible Outputs — Open-Drain Output Option Description — Electrically Erasable and Reprogrammable — Non-Volatile — Unused Product Term Shutdown Saves Power The ispLSI 2128E is a High Density Programmable Logic Device. The device contains 128 Registers, 128 Univer- • ispLSI OFFERS THE FOLLOWING ADDED FEATURES — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs sal I/O pins, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides com- plete interconnectivity between all of these elements. The ispLSI 2128E features 5V in-system programmabil- ity and in-system diagnostic capabilities. The ispLSI 2128E offers non-volatile reprogrammability of all logic, as well as the interconnect to provide truly reconfigurable systems. — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING The basic unit of logic on the ispLSI 2128E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 2128E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered.Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs — Superior Quality of Results of any GLB on the device. — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore The device also has 128 I/O cells, each of which is Tools, Timing Simulator and ispANALYZER™ directly connected to an I/O pin. Each I/O cell can be — PC and UNIX Platforms Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com November 1998 2128e_02 1 1 page Specifications ispLSI 2128E External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST COND.4 #2 DESCRIPTION1 -180 -135 -100 UNITS MIN. MAX. MIN. MAX. MIN. MAX. tpd1 A 1 Data Prop Delay, 4PT Bypass, ORP Bypass – 5.0 – 7.5 – 10.0 ns tpd2 A 2 Data Prop Delay – 7.5 – 10.0 – 13.0 ns fmax A 3 Clk Freq with Internal Feedback3 180 – 135 – 100 – MHz fmax (Ext.) fmax (Tog.) – 4 Clk Freq with External Feedback (1 tsu2 + )tco1 – 5 Clk Frequency, Max. Toggle 125 – 100 – 77.0 – 200 – 143 – 100 – MHz MHz tsu1 – 6 GLB Reg Setup Time before Clk, 4 PT Bypass 4.0 – 5.0 – 6.5 – ns tco1 A 7 GLB Reg Clk to Output Delay, ORP Bypass – 3.0 – 4.0 – 5.0 ns th1 – 8 GLB Reg Hold Time after Clk, 4 PT Bypass 0.0 – 0.0 – 0.0 – ns tsu2 – 9 GLB Reg Setup Time before Clk 5.0 – 6.0 – 8.0 – ns tco2 – 10 GLB Reg Clk to Output Delay – 3.5 – 4.5 – 6.0 ns th2 – 11 GLB Reg Hold Time after Clk 0.0 – 0.0 – 0.0 – ns tr1 A 12 External Reset Pin to Output Delay – 7.0 – 10.0 – 13.5 ns trw1 – 13 External Reset Pulse Duration 4.0 – 5.0 – 6.5 – ns tptoeen B 14 Input to Output Enable – 10.0 – 12.0 – 15.0 ns tptoedis C 15 Input to Output Disable – 10.0 – 12.0 – 15.0 ns tgoeen B 16 Global OE Output Enable – 5.0 – 7.0 – 9.0 ns tgoedis C 17 Global OE Output Disable – 5.0 – 7.0 – 9.0 ns twh – 18 External Synch Clk Pulse Duration, High 2.5 – 3.5 – 5.0 – ns twl – 19 External Synch Clk Pulse Duration, Low 2.5 – 3.5 – 5.0 – ns 1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2-0030A/2128E 5 5 Page Specifications ispLSI 2128E Part Number Description Device Family ispLSI 2128E– XXX X XXXX X Device Number Speed 180 = 180 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax Grade Blank = Commercial Package T176 = TQFP Power L = Low 0212/2128E ispLSI 2128E Ordering Information FAMILY ispLSI fmax (MHz) 180 135 100 tpd (ns) 5.0 7.5 10.0 ORDERING NUMBER ispLSI 2128E-180LT176 ispLSI 2128E-135LT176 ispLSI 2128E-100LT176 PACKAGE 176-Pin TQFP 176-Pin TQFP 176-Pin TQFP Table 2-0041/2128E 11 11 Page

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