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PDF AK2330 Data sheet ( Hoja de datos )

Número de pieza AK2330
Descripción DAC Type 8-bit 8-channelElectronic Volume
Fabricantes AKM 
Logotipo AKM Logotipo



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[AK2330]
AK2330
DAC Type 8-bit 8-channel
Electronic Volume
Features
8-bit 8 channels of built-in multiplication D/A converters
Support for external one-path, internal three-path D/A converter reference voltages
Built-in buffer amplifier with low distortion (-60dB typ.) and rail-to-rail operation
Support fo r 3V control and 5V operation bec ause of the three-wire serial system with
separate power supplies
Operating voltage range: 2.6 to 5.5V
Operating temperature range: -40 to +85°C
Package 24-pin QFNJ (4.0mm x 4.0mm x 0.75mm, 0.5-mm pitch)
Overview
The AK2330 is an electronic volume into which 8 bit 8 channels of multiplication D/A converters are
integrated on a single chip.
The reference voltage of the D/A converter can be selected from one external path (VREF pin level)
and internal three paths (VSS, AVDD, AVDD/2) for each channel and it can be used as a normal D/A
converter or an electronic volume that attenuates signals from input pins VIN0 to VIN7. A buffer
amplifier is incorporated as the subsequent stage of the D/A converter, which provides rail-to-rail
output and a signal with a distortion of -60dB.
In operational setting, the three-wire serial system, which synchronizes serial input (SDATA)
consisting of a 4-bit address and 8-bit data with the CSN and SCLK signals, is adopted, a power
supply (DVDD) is provided separately from the D/A converter, and 3V serial control and 5V D/A
converter operation are enabled. In addition, settings can be made so that the AVDD/2 level, which
was generated internally, is output to VOUT0 to VOUT7 pins through the buffer amplifier by bypassing
the D/A converter or the buffer amplifier is powered down.
A 24-pin small and low-profile QFNJ package (4.0mm square x 0.75mm height) is employed to
achieve high-density packaging.
MS0661-E-00
-1-
2 007/08
http://www.Datasheet4U.com

1 page




AK2330 pdf
[AK2330]
Pin Functions
Pin Pin
No. name
6 RSTN
7 CSN
8 SCLK
9 SDATA
10 DVDD
11 VSS
12 AVDD
13 VREF
2 VIN0
5 VIN1
14 VIN2
17 VIN3
18 VIN4
21 VIN5
22 VIN6
1 VIN7
3 VOUT0
4 VOUT1
15 VOUT2
16 VOUT3
19 VOUT4
20 VOUT5
23 VOUT6
24 VOUT7
Pin
Pin status at
type system
reset
DI Z Reset pin
Function
DI Z Chip select input pin for serial interface data
DI Z Clock input pin for serial interface data
DI
PWR
PWR
PWR
AI
Z I/O pin for serial interface data
Digital VDD power supply pin
-
Connect this pin to a 2.6 to 5.5V power supply. Connect a
bypass capacitor of 0.1μF or greater between this pin and the
VSS pin.
-
VSS power supply pin
Always apply a voltage of 0V to this pin.
Analog VDD power supply pin
Connect this pin to a 2.6 to 5.5V power supply. Connect a
- bypass capacitor of 0.1μF or greater between this pin and the
VSS pin.
Apply a voltage so that DVDD is equal to or less than AVDD.
Z D/A converter reference voltage input pin
AI L
AI L
AI L
AI L
D/A converter input pin
AI L
AI L
AI L
AI L
AO Z
AO Z
AO Z
AO Z
D/A converter/buffer amplifier output pin
AO Z
AO Z
AO Z
AO Z
Note A: Analog, D: Digital, PWR: Power, I: Input, O: Output, Z: High-Z, L: Low
MS0661-E-00
-5-
2 007/08

5 Page





AK2330 arduino
[AK2330]
Digital AC Timing
Serial interface timing
The AK2330 writes data via the three-wire synchronous se rial interface by means of CSN, SCLK,
and SDATA.
SDATA (serial data) co nsists of a r egister addr ess (startin g from the MSB, A3 to A0) and contro l
data (starting from the MSB, D7 to D0).
<1> CSN (chip select) is normally set to the high level.
When CSN is set to the low level, the serial interface becomes active.
<2> When a write operation is perf ormed, an address and data are inp ut in synchr onization with the
rising edges of 12 SCLK clock pulses while CSN is low.
<3> A write setting is made on the assumption that 12 clock pulses are input from SCLK while CSN is
low.
Note that if clock pulses more than or less tha n 12 clock p ulses are input, data ca nnot be set
correctly.
CSN
SCLK
SDATA
tCSS
tWH tWL
tCSLH
tDS tDH
A3 A2 A1 A0
D7 D6 D1 D0
tCSHH
Rising and falling times
tR tF
SCLK
VIH
VIL
Parameter Symbol
CSN setup time
SDATA setup time
SDATA hold time
SCLK high time
SCLK low time
CSN low hold time
CSN high hold time
tCSS
tDS
tDH
tWH
tWL
tCSLH
tCSHH
DAC output setting
time
tLDD
SCLK rising time
SCLK falling time
tR
tF
Condition
VOUT[7:0]=
0x100xEF
Until output reaches
the half LSB of the final
value.
RS=2.2k,
L=22k,
CL=1000pF
Min.
100
100
100
500
500
100
100
Typ.
Max.
300
100
100
Note Digital input timing measurements are made at 0.5DVDD for rising and falling edges.
Unit
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
MS0661-E-00
- 11 -
2 007/08

11 Page







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