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PDF AK1541 Data sheet ( Hoja de datos )

Número de pieza AK1541
Descripción 20 to 600MHz Delta-Sigma Fractional-N Frequency Synthesizer
Fabricantes AKM 
Logotipo AKM Logotipo



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[AK1541]
AK1541
20 to 600MHz Delta-Sigma Fractional-N Frequency Synthesizer
1. Overview
The AK1541 is a Delta-Sigma Fractional-N PLL (Phase Locked Loop) frequency synthesizer with a frequency switching
function, covering a wide range of frequencies from 20 to 600MHz. This product consists of an 18-bit Delta-Sigma
modulator, a low-noise phase frequency comparator, a highly accurate charge pump, a reference divider and a
dual-module prescaler (P/P+1).
An excellent PLL can be achieved by combining this synthesizer with the external loop filter and VCO (Voltage Controlled
Oscillator). The access to the registers is controlled via a three-lines serial interface. The operating supply voltage is from
2.7 to 5.5V; and the charge pump and serial interface can be driven by individual supply voltages.
2. Features
Delta-Sigma Fractional-N frequency synthesizer providing shorter lockup time, lower phase noise and low spurious
performance
Operating frequency:
On-chip charge pump for fast lockup
Programmable charge pump current:
20 to 600MHz
In a normal operating scheme, the charge pump current can
be set in 16 steps, in the range from 10.6 to 168.9uA.
In a fast lockup scheme, the charge pump current can be
set in 8 steps, in the range from 0.84 to 2.32mA.
Supply Voltage:
2.7 to 5.5 V (PVDD and CPVDD pins)
Separate power supply for the charge pump: PVDD to 5.5V (CPVDD pin)
On-chip power-saving features
On-chip PLL lock detect feature:
Direct output to the PFD (Phase Frequency Detector) or digital
Very low consumption current:
filtering output can be selected.
3.4mA typ. (excluding a charge pump current)
Package:
Operating temperature:
24pin QFN (0.5mm pitch, 4mm 4mm 0.7mm)
-40C° to 85C°
MS1043-E-05
1
2013/03
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AK1541 pdf
[AK1541]
Filter Schematic”. The [SWIN] pin could be open even when the first lockup feature is not used.
Note 3) Power down refers to the state where [PDN1]=[PDN2]=”Low” after power-on.
AI: Analog input pin
AO: Analog output pin AIO: Analog I/O pin DI: Digital input pin
DO: Digital output pin P: Power supply pin
G: Ground pin
24 23 22 21 20 19
CPVDD 1
18 PVDD
TEST4 2
17 RFINP
TEST1 3
LE 4
TOP
VIEW
16 RFINN
15 VREF2
DATA 5
14 DVSS
CLK
6 13 VREF1
7 8 9 10 11 12
Fig. 2 Package Pin Layout
MS1043-E-05
5
2013/03

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AK1541 arduino
[AK1541]
8. Block Functional Descriptions
1. Frequency Setup
The AK1541 is a Fractional-N type synthesizer that takes 218 as the denominator, which calculates the integer and
numerator to be set using the following formulas:
Frequency setting = Ref Frequency x (Integer + Numerator / 218)
Integer = ROUND (Target Frequency / FPFD)
Numerator = ROUND {(Target Frequency Integer x FPFD) / (FPFD / 218)}
Note) ROUND: Rounded off to the nearest value
FPFD : Phase Frequency Detector comparative Frequency([REFIN] pin input frequency/R divider ratio)
Calculation examples
Example 1) The numerator is positive when the target frequency is 465.0375MHz and the Phase Frequency Detector
comparative Frequency is 1MHz.
Integer = 465.0375MHz / 1MHz = 465.0375
It is rounded off to 465 (decimal) = 1d1 (hexadecimal) = 1 1101 0001 (binary)
Numerator = (465.0375MHz - 465 x 1MHz) / (1MHz / 218) = 9830.4
It is rounded off to 9830 (decimal) = 2666 (hexadecimal) = 10 0110 0110 0110 (binary)
Frequency setting =1MHz x (465 + 9830 / 218) = 465.0374985MHz
(In this case the error between the calculated frequency and the target frequency is 1.5Hz.)
Example 2) The numerator is negative when the target frequency is 468.550MHz and the Phase Frequency Detector
comparative Frequency is 1MHz.
Integer = 468.550MHz / 1MHz = 468.550
It is rounded off to 469 (decimal) = 1d5 (hexadecimal) = 1 1101 0101 (binary)
Numerator = (468.550MHz - 465 x 1MHz) / (1MHz / 218) = -117964.8
It is rounded off to -117965 (decimal), which is deduced from 218 to be converted into binary for 2's complementary
expression.
218 - 117965 (decimal) = 144179 (decimal) = 23333 (hexadecimal) = 10 0011 0011 0011 0011 (binary)
Frequency setting =1MHz x (469 + (-117965/218)) = 468.5499992MHz
(In this case the error between the calculated frequency and the target frequency is 0.8Hz.)
Calculation of 2’s complement representation
1) Positive number: Binary expression (Unmanipulated)
exp. 100 (decimal) = 64 (hexadecimal) = 110 0100
(binary)
2) Negative number: 218 minus this number in binary expression
exp. 100 (decimal)
218 - 100 = 262044 (decimal) = 3FF9C (hexadecimal) = 11 1111 1111 1001 1100 (binary)
MS1043-E-05
11
2013/03

11 Page







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