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PDF MP1009 Data sheet ( Hoja de datos )
| Número de pieza | MP1009 | |
| Descripción | Half-Bridge and Push-Pull CCFL Inverter Controller | |
| Fabricantes | MPS | |
| Logotipo |  |
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MP1009
Nu-PulseTM, Half-Bridge and Push-Pull
CCFL Inverter Controller
The Future of Analog IC Technology
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION – INTERNAL USE ONLY
DESCRIPTION
The MP100 9 is a fixe d operating frequency
inverter controller that controls t wo external
power MOSFETs in Nu-Pulse TM, Half-Bridge or
Push-Pull configuration for powering one or
more cold cathode fluor escent lamps (CCFL) to
backlight liquid crystal displays (LCD).
The MP1009 offers cost effective solutions with
minimized external components. Th e controller
provides high efficiency power conversion of
unregulated DC input voltages to nearly pur e
sine waves. The featured fault detection and
protection scheme (patent pendin g) includes
open lamp regulation, open lamp protection and
short lamp protection.
Burst mode dimming is controlled w ith either an
external analog or digital signal. Lam p voltages
and lamp currents are continuously regulated
under any operating conditions.
The MP100 9 is available in a 16-pin SOIC
package.
FEATURES
• Drives Two Exter nal, L ow Co st, N -Channel
MOSFETs
• Fixed Operating Frequency
• Input Voltage Range of 8V to 30V
• Lamp Current and Voltage Regulation
• Burst Mode Dimming Control
• Integrated Burst Mode Ocsillator andModulator
• Soft-On and Soft-Off Burst Envelope
• Open Lamp & Short circuit Protection
• Fault Timer and Indicator
• Available in SOIC 16 Package
APPLICATIONS
• Desktop LCD Flat Panel Displays
• Flat Panel Video Displays
• LCD TVs and Monitors
"MPS", "The Future of Analog IC Technology", and "Nu-Pulse" are Trademarks
of Monolithic Power Systems, Inc.
MP1009 and Nu-Pulse configuration are MPS proprietary technologies covered
by US Patents:
6,683,422
6,114,814
6,316,881
7,161,305
Other patents are pending.
TYPICAL APPLICATION
OV2
LI1
LI2
C11
C12
R9
C14
R11 R10
C13
MP1009
OV2 OV1
OV1
LI1
LI2
COMP
R12
C9
REF
FT
FSET
BOSC
R13
C10
DBRT
R14
C18
VIN
REF
R5 R8 R7 R6
R18
OV1
R19
OV2
C15 R15
LV1 LI2 LI1
R16
LV4
LV2 D4
R17
D3
OL1 OL4 OL2 OL3
LV3
C1
LV1
C2
OL1
R1
C3
LV2
C4
OL2
R2
C5
LV3
C6
OL3
R3
C7
LV4
C8
OL4
R4
MP1009 Rev. 0.91
5/12/2008
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
1
http://www.Datasheet4U.com
1 page  
MP1009 – NU-PULSETM CCFL INVERTER CONTROLLER
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION – INTERNAL USE ONLY
PIN FUNCTIONS
Pin # Name
1 OV2
2 LI1
3 LI2
4 COMP
5 FT
6 FSET
7 BOSC
8 DBRT
9 VIN
10 BT
11 TG
12 SW
Description
Open lam p voltage feedb ack input 2. Con nect this pin to the tap of a cap divider and a bias
resistor to VCC for lamp voltage feed ba ck. In multi-lamp application, connect this pin through a
diode in “or” relationship to all lamp voltage feed back points, which are AC in phase.
If the peak voltage value at OV2 pin e xceeds +11.5 V, the control ler treat s this as lamp ove r-
voltage condition. A pulse of current will pull-do wn the COMP pin voltage to regulate the lamp
voltage. The burst dimming signal is ignored and the Fault Timer starts ramping up.
This signal is also use d for short circuit prot ection. If the voltage at OV2 is always above 4.9V,
the controller will treat this as a short circuit condition after a certain delay. The Fault Timer will
start ramping up. In single lamp application, connect OV1and OV2 pins together.
Lamp curren t feedback 1. Conn ect this pin to the cu rrent sense re sistor. In multi-lamp
application, connect this pin through a diode in “and” relationship to call lamp current feed back
points, which are A C in phase. Combined with the lamp current feedback signal from LI2, the
signal is fed t o the internal error a mplifier. Selecting the feedback resistors can easily program
the lamp current.
The signal is also used for open lamp protection. If the voltage at L I1 is always below 1.1V, the
controller treats this a s an open l amp condition after a ce rtain delay. The bu rst dimming signal
is ignored and the Fault Timer starts ramping up. In single lamp application, short LI1 to LI2 pin
and connect to the lamp current feedback resistor through a small RC filter.
Lamp current feedback 2. The function of this pin is same as LI1. In multi-lamp application, this
pin is used for lamp current feedback which is out-of-phase of LI1.
Feedback Compensation Node. Connect a compensation capacitor from this pin to GND.
This pin is also used for IC enable control. A logic low (below 0.5V) input turns off the IC. The
enable logic input signal should have open collector (OC) structure.
Fault Indicator. Connect a capacitor from this pin to GND to program the open lamp and short
lamp protection delay time. When the voltage on this pin reaches 1.2V, the IC is shutdown until
it is enabled again.
Switching Frequency Set. Connect a resistor from this pin to GND. This resistor sets the
operating frequency of the MP1009.
Burst Repetition Rate Setting. For DC input internal burst dimming, connect a resistor and a
capacitor from this pin to GND. The burst dimming frequency and minimum dimming duty is
programmed by the resistor and capacitor values. For external logic PWM input dimming,
connect BOSC to VCC and apply the logic signal to the DBRT pin.
Burst-Mode (Digital) Brightness Control Input. For DC input internal burst dimming, the voltage
range of 0V to 1.2V at DBRT linearly sets the burst-mode duty cycle from minimum to 100%.
For external logic PWM input dimming, drive DBRT pin higher than 2.2V and lower than 1.6V to
directly control the inverter dimming duty. If burst dimming is not used, connect DBRT to VCC.
Input Power Rail. Decouple this pin to GND with >1µF ceramic capacitor. It is desirable to add a
10Ω resistor between VIN pin and the input bus.
Output Bootstrap. BT provides gate driver bias for the high-side MOSFET. Connect a capacitor
from BT to SW.
High-Side MOSFET Gate Output. Connect TG to the gate of the high-side, external power
MOSFET.
Bridge Output. Connect SW to the source of the high-side MOSFET and the drain of the
low-side MOSFET.
MP1009 Rev. 0.91
5/12/2008
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
5
5 Page 
MP1009 – NU-PULSETM CCFL INVERTER CONTROLLER
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION – INTERNAL USE ONLY
TYPICAL APPLICATION CIRCUIT
OV2
MP1009
OV2 OV1
OV1
LI1 LI1
LI2
C11
3.3nF/50V
C12 1uF/16V
R9 97.6k/1%
R11
C1468nF/50V
R10 221k/1%
10k
C13
0.1uF/50V
LI2
COMP
FT
FSET
BOSC
DBRT
R12
C9 1uF/16V 3
REF
R13
C10
3
100nF/50V
R14
10k
REF
C15 R15
220uF/25V10k
C18
1uF/25V
VIN
R5 R8 R7 R6
10k 10k 10k 10k
R18
OV1
2k
BAV70
R19
OV2
2k
BAV70
LV1
LV4
LV2
LV3
LI2
R16 2k
BAW56
D4
LI1
R17
BAW56
2k
D3
OL1 OL4 OL2 OL3
LV1
C1
8pF/3kV
C2
2.2nF/50V
OL1
R1
374/1%
LV2
C3
8pF/3kV
OL2
C4
2.2nF/50V
R2
374/1%
LV3
C5
8pF/3kV
OL3
C6
2.2nF/50V
R3
374/1%
LV4
C7
8pF/3kV
OL4
C8
2.2nF/50V
R4
374/1%
MP1009 Rev. 0.91
4/15/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MP1009.PDF ] | |
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