PDF PBL3796-2 Data sheet ( Hoja de datos )

Número de pieza	PBL3796-2
Descripción	Subscriber Line Interface Circuit
Fabricantes	Ericsson
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No Preview Available ! April 1997 www.DataSheet4U.com PBL 3796, PBL 3796/2 Subscriber Line Interface Circuit Description Key Features PBL 3796 is an analog Subscriber Line Interface Circuits (SLICs), which are fabrica- ted in a 75 V bipolar, monolithic process. The programmable battery feed is resistive with short-loop current limiting. A switch-mode regulator reduces on-chip power dissipation in the active state. In the standby state, power dissipation is further reduced, while still permitting supervisory functions to be active. Tip-ring polarity is reversible without altering SLIC supervisory and voice frequency (vf) functions. Tip and ring outputs can be set to high impedance states. These and other operating states are activated via a parallel, four bit control word. An external resistor controls the off-hook detector threshold current. The ring trip detector can operate with both balanced and unbalanced ringing systems. The two detectors are read via a shared output. Ring and test relay drivers with internal clamp diodes are provided. The complex or real two-wire impedance is set by a scaled, lumped element network. Two- to four-wire and four- to two-wire signal conversion is provided by the SLIC in conjunction with either a conventional or a programmable CODEC/filter. Longitudinal line voltages are suppressed by a control loop within the SLIC. Packages are 28-pin, dual-in-line; 32-pin or 44-pin j-leaded chip carrier. The difference between PBL 3796 and PBL 3796/2 is mainly the longitudinal balance spec. 4 RINGRLY 5 TESTRLY 26 DR 25 DT 27 TIPX 22 HPT 23 HPR 28 RINGX 2 VREG L VBAT GND2 6 7 1 Ring Relay Driver Test Relay Driver Ring Trip Comparator Two-wire Interface Input Decoder and Control Loop Detector VF Signal Transmission Line Feed Controller and Longitudinal Suppression Switching Regulator 91 8 0 CHS VQBAT CHCLK 3 VCC 20 VEE 16 C1 14 C2 15 C3 11 C4 12 E0 13 DET 24 RD 21 VTX 19 RSN 17 RDC 18 GND1 • On-chip switch mode regulator to minimize power dissipation • Programmable, resistive battery feed with short-loop current limiting • Line feed characteristics independent of battery variations • Tip-ring polarity reversal function • Tip and ring open circuit state; tip open with ring active state • Detectors: - programmable loop current detector - ring trip detector • Ring and test relay drivers • Line terminating impedance, complex or real, set by a simple external network • Hybrid function with conventional or programmable CODEC/filters • 70 dB longitudinal to metallic balance • 79 mA peak longitudinal current suppression • Idle noise < 10 dBrnC, < -80 dBup PBL 3796 379P6BL Figure 1. Block diagram. Pin numbers refer to the dual-in-line package. 4-105 http://www.Datasheet4U.com/ 1 page PBL 3796 Paramewtewrw.DataSheet4U.com Polarity reversal time, tpol TIPX idle voltage, VTi TIPX to RINGX idle voltage, Vtro Standard version -/2 version 4-wire transmit port (VTX) Overload level, VTXO Output offset voltage, ∆VTX Output impedance, ZTX 4-wire receive port (RSN) RSN dc voltage, VRSN RSN impedance, Z RSN RSN current (IRSN) to metallic loop current (IL) gain, αRSN Frequency response Two-wire to four-wire, g2-4 Four-wire to two-wire, g4-2 Four-wire to four-wire, g4-4 Insertion loss Two-wire to four-wire, G 2-4 Four-wire to two-wire, G4-2 Four-wire to four-wire, G4-4 Gain tracking Two-wire to four-wire (Note 7) and Four-wire to two-wire (Note 8) Ref fig Conditions Normal to reversed polarity or reversed to normal polarity Normal polarity VBat = -48 V Active and standby VBat=-48V R1=open loop Normal polarity Reversed polarity Normal polarity Reversed polarity Min -5.0 -42 -40 Typ 4 -3.5 Max 15 -2.0 42 40 Unit ms V V V V V 2 Load impedance > 20 kΩ, f = 1 kHz, 1% THD, E = 0 RX Note 6 0.2kHz ≤ f ≤ 3.4kHz 3.1 3.5 9.0 10.1 VPk dBu -50 ±5 +50 mV 6 20 Ω IRSN = 0 0.2kHz ≤ f ≤ 3.4kHz 0.2kHz ≤ f ≤ 3.4kHz, αRSN = IL IRSN -10 0 +10 mV 3 20 Ω 40 dB 6 0.3kHz ≤ f ≤ 3.4kHz Relative to 1.0 kHz, 0 dBu ERX = 0 V, (Note 7) 6 0.3kHz ≤ f ≤ 3.4kHz Relative to 1.0 kHz, 0 dBu EL = 0 V, (Notes 8, 14) 6 0.3kHz ≤ f ≤ 3.4kHz Relative to 1.0 kHz, 0 dBu EL = 0 V, (Notes 8, 14) -0.1 ±0.03 +0.1 dB -0.1 ±0.03 +0.1 dB -0.1 ±0.06 +0.1 dB 6 0 dBu, 1 kHz, E = 0, (Notes 7, 9) -0.15 RX 6 0 dBu, 1 kHz, EL = 0, (Notes 8, 9) -0.15 6 0 dBu, 1 kHz, EL = 0, (Notes 8, 9) -0.15 ±0.1 +0.15 dB ±0.1 +0.15 dB ±0.1 +0.15 dB 6 Referenced to -10 dBu, 1 kHz +3 dBu to -30 dBu -30 dBu to -55 dBu -0.1 +0.1 dB ±0.1 dB C TIPX VTX TX + 27 21 + RL VTR ILdc PBL3796, PBL 3796/2 RT E RX VTX Figure 6. Frequency response, insertion loss, gain tracking, idle channel noise, EL – RINGX 28 RSN 19 RX RRX – THD, inter-modulation. 1/ωC << RL, RL = 600 Ω, RT = 60 kΩ, RRX = 30 kΩ. 4-109 http://www.Datasheet4U.com/ 5 Page PBL 3796 44PLwCwCw3.D2PaLtaCSChePeDtI4PU.comSymbol 34 25 22 HPT Description Tip side (HPT) of ac/dc separation capacitor. 35 26 23 HPR Ring side (HPR) of ac/dc separation capacitor. 36 — — NC No internal connection. Note 1. 37 27 24 RD 38 28 25 DT Loop current detector programming resistor, RD, connects from RD to VEE. A filter capacitor CD may be connected from RD to GND1. Inverting ring trip comparator input. 39 — — NC No internal connection. Note 1. — 29 — TP 40 30 26 DR TP is a thermal conduction pin tied to substrate (QBat). Note 3. Non-inverting ring trip comparator input. 41 — — TIPXsense TIPXSense is internally connected to TIPX. TIPXSense is used during manufacturing, but requires no connection in SLIC applications, i.e. leave open. 42 31 27 TIPX The TIPX pin connects to the tip lead of the 2-wire line interface via overvoltage protec- tion components, ring and test relays. 43 32 28 RINGX The RINGX pin connects to the ring lead of the 2-wire line interface via overvoltage protection components, ring and test relays. 44 — — RINGXSense Notes RINGXSense is internally connected to RINGX. RINGXSense is used during manufacturing, but requires no connection in SLIC applications, i.e. leave open. 1. The GND1 and GND2 pins should be connected together via a direct printed circuit board trace. 2. Pins marked NC are not internally connected. It is recommended to connect these pins to ground. 3. For 32 pin PLCC, these pins (5 and 29) should be connected to V , heatsink. Bat TESTRLY 7 L8 NC 9 VBAT 10 VQBAT 11 CHS 12 NC 13 CHCLK 14 NC 15 C4 16 NC 17 44 PLCC 39 NC 38 DT 37 RD 36 NC 35 HPR 34 HPT 33 NC 32 VTX 31 VEE 30 NC 29 RSN TP 5 TESTRLY 6 L7 VBAT 8 VQBAT 9 CHS 10 CHCLK 11 C4 12 NC 13 32 PLCC 29 TP 28 DT 27 RD 26 HPR 25 HPT 24 VTX 23 VEE 22 RSN 21 GND1 GND2 1 VREG 2 VCC 3 RINGRLY 4 TESTRLY 5 L6 VBAT 7 VQBAT 8 CHS 9 CHCLK 10 C4 11 E0 12 DET 13 C2 14 28 RINGX 27 TIPX 26 DR 25 DT 24 RD 23 HPR 22 HPT 21 VTX 20 VEE 19 RSN 18 GND1 17 RDC 16 C1 15 C3 Figure 10. Pin configuration, top view. 32-pin or 44-pin j-leaded chip carrier (32 PLCC, 44 PLCC) and 28-pin dual-in-line. 4-115 http://www.Datasheet4U.com/ 11 Page

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