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Número de pieza GD5F1GQ4UAY
Descripción SPI (Serial Peripheral Interface) NAND Flash Memory
Fabricantes GigaDevice 
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SPI (*1/*2/*4) NAND Flash
GD5F1GQ4UAY
SPI (Serial Peripheral Interface) NAND Flash Memory
FEATURE
1G-bit Serial NAND Flash
-128M-byte
-2048 bytes page for read and program, spare 128bytes
-128K bytes per block for erase
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3
Program/Erase/Read Speed
-Page Program time: 300us typical
-Block Erase time: 3.5ms typical
-Page read time: 25us maximum(w/o ECC)
-Page read time: 25+60us maximum(w/I ECC)
Low Power Consumption
-60mA maximum active current
-70uA typical standby current
High Speed Clock Frequency
-104MHz for fast read with 30PF load
-Quad I/O Data transfer up to 320Mbits/s
-2176/2048/64/16 wrap read option
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top or Bottom, Block selection combination
Advanced security Features
-16-Bit Customer ID
-8K-Byte OTP Region
Enhanced access performance
-2K bytes cache for fast random read
-Cache read and cache program
Assistant Block Management
-Bad Block Protection
-Bad Block Inhibit(BBI)
Advanced Feature for NAND
-Internal ECC option, per 512bytes
-NOP (partial program) is 4
-Internal data move by page with ECC
-Promised golden block0
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
-Full voltage range:1.62~1.95V
Minimum 100,000 Program/Erase Cycles
Data retention: 20 yeas
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GD5F1GQ4UAY pdf
SPI (*1/*2/*4) NAND Flash
GD5F1GQ4UAY
DEVICE OPERATION
SPI Modes
SPI NAND supports two SPI modes:
• CPOL = 0, CPHA = 0 (Mode 0)
• CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All
timing diagrams shown in this data sheet are mode 0.
Figure2. SPI Modes Sequence Diagram
CPOL CPHA
0 0 SCLK
1 1 SCLK
SI
SO
CS#
MSB
LSB
MSB
LSB
Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3). Do not begin toggling SCLK until after
CS# is driven LOW.
Standard SPI
SPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select
(CS#), Serial Data Input (SI) and Serial Data Output (SO).
Dual SPI
SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow
data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command
the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1.
Quad SPI
SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow
data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command
the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1, and WP# and HOLD# pins become SIO2 and SIO3.
5
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GD5F1GQ4UAY arduino
SPI (*1/*2/*4) NAND Flash
GD5F1GQ4UAY
Page Read to Cache (13H)
Figure8. Page Read to cache Sequence Diagram
CS#
SCLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
Command
13H
High-Z
24-bit address
23 22 21
3210
CS#
SLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
tCS Get Feature
1 byte address
0FH
76543210
High-Z
MSB
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO 7 6 5 4 3 2 1 0 7
MSB
Page Read (to buffer) (13H+24-bit address+31H)
Next Page Read (31H)
Last Page Read (3FH)
The Page Read (to buffer) and Next Page Read and Last Page Read command can be used to increase READ
operation speed when accessing sequential pages.
A normal PAGE READ (13H+24-bit address) command sequence is issued (see Figure 8 for details). The device is
busy for tRD time during the time it takes to transfer the first page of data from the memory to the data register. Following a
status of successful completion, the Page Read (to buffer) or Next Page Read (31H) command is latched into the
command register. The device is busy for tDCBSYR1 while data is being transferred from the data register to the cache
register. When the data register contents are transferred to the cache register, another Page Read is automatically started
as part of the Page Read (to buffer) or Next Page Read (31H) command. Data is transferred from the memory array to the
data register at the same time data is being output (RANDOM DATA READ 03H/0BH/3BH/6BH/BBH/EBH) from the cache
register. If the total time to output data exceeds tRD, then the PAGE READ is hidden. The second and subsequent pages of
data are transferred to the cache register by issuing additional Page Read (to buffer) or Next Page Read(31H) command.
The device is busy for tDCBSYR1. This time can vary, depending on whether the previous memory-to-data-register
transfer was completed before issuing the next Page Read (to buffer) or Next Page Read (31H) command. If the data
transfer from memory to the data register is not completed before the Page Read (to buffer) or Next Page Read (31H)
command is issued, the device is busy until the transfer is complete. It is not necessary to output a whole page of data
11
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