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PDF 25L5121E Data sheet ( Hoja de datos )
| Número de pieza | 25L5121E | |
| Descripción | MX25L5121E | |
| Fabricantes | MXIC | |
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MX25L5121E
MX25L1021E
MX25L5121E, MX25L1021E
DATASHEET
P/N: PM1573
REV. 0.01, APR. 07, 2010
1
Free Datasheet http://www.Datasheet4U.com
1 page  
- Serial Data Input
• SO Output
- Serial Data Output
• WP# pin
- Hardware write protection
• PACKAGE
- 8-pin SOP (150mil)
- 8-pin TSSOP (173mil) for MX25L5121E only
- All Pb-free devices are RoHS Compliant
MX25L5121E
MX25L1021E
GENERAL DESCRIPTION
The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access
to the device is enabled by CS# input.
The device provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the spec-
ified page or sector locations will be executed. Program command is executed on page (32 bytes) basis, and erase
command is executes on sector, or block, or whole chip.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in Standby Mode and draws less than 30uA (typical:20uA)
DC current.
The device utilizes Macronix proprietary memory cell, which reliably stores memory contents even after typical
100,000 program and erase cycles.
P/N: PM1573
REV. 0.01, APR. 07, 2010
5
Free Datasheet http://www.Datasheet4U.com
5 Page 
MX25L5121E
MX25L1021E
COMMAND DESCRIPTION
Table 3. Command Set
Command WREN (write WRDI (write
(byte)
enable)
disable)
1st byte 06 (hex)
04 (hex)
WRSR
RDID
RDSR
(write status (read identific- (read status
register)
ation)
register)
01 (hex)
9F (hex)
05 (hex)
2nd byte
3rd byte
4th byte
5th byte
Action
sets the (WEL) resets the to write new outputs to read out
write enable (WEL) write values of the JEDEC
the values
latch bit enable latch status register ID: 1-byte of the status
bit Manufacturer register
ID & 2-bytes
Device ID
READ (read
data)
03 (hex)
AD1
(A23-A16)
AD2
(A15-A8)
AD3
(A7-A0)
n bytes read
out until CS#
goes high
FAST READ
(fast read
data)
0B (hex)
AD1
AD2
AD3
Dummy
n bytes read
out until CS#
goes high
Command
(byte)
1st byte
2nd byte
3rd byte
4th byte
Action
SE (sector
erase)
BE (block
erase)
CE (chip
erase)
PP (page
program)
20 (hex) 52 or D8 (hex) 60 or C7 (hex) 02 (hex)
AD1 AD1
AD1
AD2 AD2
AD2
AD3 AD3
AD3
to erase the to erase the to erase to program
selected
selected whole chip the selected
sector
block
page
DP (Deep
power down)
RDP (Release
from deep
power down)
B9 (hex)
AB (hex)
enters Deep release from
Power Down Deep Power
Mode
Down Mode
Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially
enter the hidden mode.
Note 2: Value "1" should be input to the un-used significant bits of address bits by user (e.g. A17~A23(MSB) in
MX25L1021E ; A16-A23(MSB) in MX25L5121E)
P/N: PM1573
11
REV. 0.01, APR. 07, 2010
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 41 Páginas | |
| PDF Descargar | [ Datasheet 25L5121E.PDF ] | |
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