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PDF K4N51163QC Data sheet ( Hoja de datos )

Número de pieza K4N51163QC
Descripción 512Mbit gDDR2 SDRAM
Fabricantes Samsung 
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K4N51163QC
512M gDDR2 SDRAM
512Mbit gDDR2 SDRAM
Revision 1.8
October 2006
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev 1.8 Oct. 2006
Free Datasheet http://www.Datasheet4U.com

1 page




K4N51163QC pdf
K4N51163QC
5.0 PACKAGE DIMENSIONS (84 Ball FBGA)
11.00 ± 0.10
6.40
0.80 1.60
987654321
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
84-0.45±0.05
0.2 M A B
3.20
(0.90)
(1.80)
(6.15)
512M gDDR2 SDRAM
# A1 INDEX MARK (OPTIONAL)
11.00 ± 0.10
#A1
-5-
0.35±0.05
MAX.1.20
Unit : mm
Rev 1.8 Oct. 2006
Free Datasheet http://www.Datasheet4U.com

5 Page





K4N51163QC arduino
K4N51163QC
512M gDDR2 SDRAM
9.3 Timing Parameters by Speed Grade
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Symbol
tAC
tDQSCK
tCH
tCL
- 25
min max
-400 +400
-350 +350
0.45 0.55
0.45 0.55
CK half period
Clock cycle time, CL= x
tHP min(tCL, x
tCH)
tCK 2.5 8.0
DQ and DM input hold time
tDH 125
x
DQ and DM input setup time
tDS 50
Control & Address input pulse width for
each input
DQ and DM input pulse width for each
input
tIPW
tDIPW
0.6
0.35
Data-out high-impedance time from CK/
CK
tHZ
x
DQS low-impedance time from CK/CK
tLZ
(DQS)
tAC
min
DQ low-impedance time from CK/CK tLZ(DQ)
DQS-DQ skew for DQS and associated
DQ signals
tDQSQ
2*tAC
min
x
DQ hold skew factor
tQHS
x
DQ/DQS output hold time from DQS
Write command to first DQS latching
transition
tQH tHP -
tQHS
tDQSS -0.25
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS falling edge to CK setup time
tDSS
DQS falling edge hold time from CK
tDSH
Mode register set command cycle time tMRD
Write postamble
tWPST
Write preamble
tWPRE
0.35
0.35
0.2
0.2
2
0.4
0.35
Address and control input hold time
tIH 250
x
x
x
tAC
max
tAC
max
tAC
max
200
300
x
0.25
x
x
x
x
x
0.6
x
x
Address and control input setup time
Read preamble
Read postamble
Active to active command period for
1KB page size products
Active to active command period for
2KB page size products
tIS
tRPRE
tRPST
tRRD
175
0.9
0.4
7.5
tRRD 10
x
1.1
0.6
x
x
(Refer to notes for informations related to this table at the bottom)
- 2A
min max
- 33
min max
- 36
Units Notes
min max
-450 +450 -470 +470 -500 +500 ps
-400 +400 -420 +420 -450 +450 ps
0.45 0.55 0.45 0.55 0.45 0.55 tCK
0.45 0.55 0.45 0.55 0.45 0.55 tCK
min min min
(tCL, x (tCL, x (tCL, x ps 20,21
tCH)
tCH)
tCH)
2.86 8.0 3.3 8.0 3.6 8.0 ns 24
175
x 195
x 225
x
ps
15,16,
17
50
x 70
x 100
x
ps
15,16,
17
0.6 x 0.6 x 0.6 x tCK
0.35 x 0.35 x 0.35 x tCK
x
tAC
max
x
tAC
max
x
tAC
max
ps
tAC tAC
min max
tAC tAC
min max
tAC
min
tAC
max
ps
27
2*tAC tAC 2*tAC tAC 2* tAC tAC
min max min max min max
ps
27
x 310
x 320
x 340 ps 22
x
tHP -
tQHS
WL
-0.25
0.35
0.35
0.2
0.2
2
0.4
0.35
325
200
0.9
0.4
410
x
WL
+0.25
x
x
x
x
x
0.6
x
x
x
1.1
0.6
x
tHP -
tQHS
WL
-0.25
0.35
0.35
0.2
0.2
2
0.4
0.35
345
220
0.9
0.4
420
x
WL
+0.25
x
x
x
x
x
0.6
x
x
x
1.1
0.6
x
tHP -
tQHS
WL
-0.25
0.35
0.35
0.2
0.2
2
0.4
0.35
375
250
0.9
0.4
440
x
WL
+0.25
x
x
x
x
x
0.6
x
x
x
1.1
0.6
ps 21
ps
tCK
tCK
tCK
tCK
tCK
tCK
tCK 19
tCK
ps
14,16,
18
ps
14,16,
18
tCK 28
tCK 28
7.5 x 7.5 x 7.5 x ns 12
10 x 10 x 10 x ns 12
- 11 -
Rev 1.8 Oct. 2006
Free Datasheet http://www.Datasheet4U.com

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