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PDF RT5350 Data sheet ( Hoja de datos )
| Número de pieza | RT5350 | |
| Descripción | IEEE 802.11n draft compliant 1T1R MAC/BBP/PA/RF | |
| Fabricantes | Ralink | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de RT5350 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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RT5350
Preliminary Datasheet
PreliminaryDatNovember 25, 2010
Introduction
The RT5350 SoC combines Ralink’s IEEE 802.11n draft compliant 1T1R MAC/BBP/PA/RF, a high
performance 360 MHz MIPS24KEc CPU core, a 5-port integrated 10/100 Ethernet switch/PHY and a USB
host/device. With the RT5350, there are very few external components required for 2.4 GHz 802.11n
wireless products. The RT5350 employs Ralink’s 2nd generation 802.11n technologies for longer range
and better throughput. The embedded, high performance CPU can easily manage advanced applications
such as Wi-Fi data processing without overloading the host processor. In addition, the RT5350 offers a
variety of hardware interfaces (SPI/I2S/I2C/PCM/UART/USB) to support a range of possible applications.
Applications
iNIC
Features
Embedded 1T1R 2.4G CMOS RF
Embedded 802.11n 1T1R MAC/BBP with
MLD enhancement
Embedded PA/LNA
150 Mbps PHY data rate
20 Mhz/40 MHz channel width
Legacy and high throughout modes
Compressed block ACK
Bluetooth Co-existence
Multiple BSSID (up to 16)
WEP64/128, WPA, WPA2, WAPI engines
QOS - WMM, WMM Power Save
Hardware frame aggregation
Supports 802.11h TPC
Functional Block Diagram
AP/Router
MIPS 24KEc 360 Mhz with 32 KB I cache/16
KB D cache
Supports 16-bit SDR SDRAM (up to 64 MB)
Supports boot from ROM, FLASH
USB 2.0 HOST/Device dual mode x1
Embedded 5-port 10/100 Mbps Ethernet
switch and 5-port UTP PHY
Supports 5 10/100 UTP ports
Slow speed I/O : GPIO, SPI, I2C, I2S, PCM,
UART, and JTAG
Packaging and I/O voltage
12 mm x 12 mm TFBGA-196 package
I/O: 3.3 V I/O
40/20 MHz
Crystall
Clock/Timer/Reset/PLL
SDRAM/
Controller
16bit SDRAM
1T2R
Diversity
802.11n
1T1R
2.4 GHz
RF
802.11n
1T1R
MAC
BBP
MIPS 24KEc
(360 MHz)
32K I-Cache
16K D-Cache
UART Full+Lite
USB 2.0
Host/Device PHY
I2C
UART Interface
USB 2.0 Interface
EEPROM/Control
FE
TRroauntsefor rm
er
Fast Ethernet Switch
01234
I2S
SPI
PCM
External Interface
Audio Interface
SLIC
Codec
GPIO/LED
Order Information
Ralink Technology Corp. (USA)
Suite 200
20833 Stevens Creek Blvd.
Cupertino, CA95014
Tel: 408-725-8070
Fax: 408-725-8069
Ralink Technology Corp. (Taiwan)
5F. 36 Taiyuan St,
Jhubei City, Hsin-Chu
Taiwan, R.O.C
Tel: 886-3-560-0868
Fax: 886-3-560-0818
Part Temp
Number Range
RT5350F -10~
55 0C
Packaging
Green/RoHS
Compliant
TFBGA 196 ball
(12 mm x 12
mm)
DSRT5350_V1.0_112510
Form No.：QS-073-F02
Rev.：1
Kept by： DCC
-1-
Ret. Time： 5 Years
Free Datasheet http://www.Datasheet4U.com
1 page  
Table of Figures
RT5350
Preliminary Datasheet
PreliminaryDatNovember 25, 2010
FIGURE 2-1 SDRAM INTERFACE .................................................................................................................................. 16
FIGURE 2-2 POWER-ON SEQUENCE .............................................................................................................................. 17
FIGURE 3-1 RT5350 BLOCK DIAGRAM ......................................................................................................................... 18
FIGURE 3-2 MIPS 24KEC PROCESSOR DIAGRAM ............................................................................................................ 21
FIGURE 3-3 SYSTEM CONTROL BLOCK DIAGRAM ............................................................................................................. 22
FIGURE 3-4 TIMER BLOCK DIAGRAM ............................................................................................................................. 33
FIGURE 3-5 INTERRUPT CONTROLLER BLOCK DIAGRAM .................................................................................................... 37
FIGURE 3-6 UART BLOCK DIAGRAM............................................................................................................................. 43
FIGURE 3-7 UART LITE BLOCK DIAGRAM ...................................................................................................................... 50
FIGURE 3-8 PROGRAM I/O BLOCK DIAGRAM.................................................................................................................. 56
FIGURE 3-9 1 I2C CONTROLLER BLOCK DIAGRAM ............................................................................................................ 62
FIGURE 3-10 PCM CONFIGURATION EXAMPLE 1 ............................................................................................................ 75
FIGURE 3-11 PCM CONFIGURATION EXAMPLE 2 ............................................................................................................ 76
FIGURE 3-12 PCM CONFIGURATION EXAMPLE 3 ............................................................................................................ 76
FIGURE 3-13 GENERIC DMA CONTROLLER BLOCK DIAGRAM............................................................................................. 77
FIGURE 3-14 SPI CONTROLLER BLOCK DIAGRAM ............................................................................................................ 82
FIGURE 3-15 WAVEFORM OF SPI INTERFACE.................................................................................................................. 87
FIGURE 3-16 I2S TRANSMITTER BLOCK DIAGRAM............................................................................................................ 88
FIGURE 3-17 I2S TRANSMITTER/RECEIVER ..................................................................................................................... 88
FIGURE 3-18 SRAM/SDRAM CONTROLLER BLOCK DIAGRAM .......................................................................................... 92
FIGURE 3-19 USB HOST CONTROLLER & PHY BLOCK DIAGRAM........................................................................................ 97
FIGURE 3-20 PDMA TX DESCRIPTOR FORMAT ............................................................................................................. 100
FIGURE 3-21 PDMA RX DESCRIPTOR FORMAT............................................................................................................. 101
FIGURE 3-22 BULK-OUT AGGREGATION FORMAT .......................................................................................................... 101
FIGURE 3-23 FRAME ENGINE BLOCK DIAGRAM............................................................................................................. 108
FIGURE 3-24 PDMA FIFO-LIKE RING CONCEPT ........................................................................................................... 109
FIGURE 3-25 PDMA TX DESCRIPTOR FORMAT ............................................................................................................. 110
FIGURE 3-26 PDMA RX DESCRIPTOR FORMAT............................................................................................................. 110
FIGURE 3-27 ETHERNET SWITCH BLOCK DIAGRAM ........................................................................................................ 121
FIGURE 3-28 DOUBLE TAG........................................................................................................................................ 161
FIGURE 3-29 SPECIAL TAG ........................................................................................................................................ 161
FIGURE 3-30 PACKET CLASSIFICATION, QOS, SCHEDULING, AND BUFFER CONTROL ............................................................. 163
FIGURE 3-31 802.11N 1T1R MAC/BBP BLOCK DIAGRAM ........................................................................................... 165
FIGURE 3-32 802.11N 3T3R MAC/BBP REGISTER MAP ............................................................................................. 166
FIGURE 3-33 TX FRAME INFORMATION ....................................................................................................................... 207
FIGURE 3-34 TX DESCRIPTOR FORMAT........................................................................................................................ 208
FIGURE 3-35 TXWI FORMAT .................................................................................................................................... 209
FIGURE 3-36 RX DESCRIPTOR RING ............................................................................................................................ 210
FIGURE 3-37 RX DESCRIPTOR FORMAT........................................................................................................................ 211
FIGURE 3-38 RXWI FORMAT .................................................................................................................................... 212
DSRT5350_V1.0_112510
Form No.：QS-073-F02
Rev.：1
Kept by： DCC
-5-
Ret. Time： 5 Years
Free Datasheet http://www.Datasheet4U.com
5 Page 
Pin Name
Ground pins: 51 pins
A1, A4,B2,B4,
C2,C3,C4,C5,
D2, D3,D4,D5,
D6,D7,D8,D9,
E2,E4,E5,E6,
E7,E8,E9, F1,
F2,F3,F4,F6,
F7,F8,G6,G7,
G8,H6,H7,H8,
J6,J7,J8,J9,
K9,K10,L10,M10,
M11,M12,N10,N13,
N14,P10,P14
GND
RT5350
Preliminary Datasheet
PreliminaryDatNovember 25, 2010
I/O/IPU/IPD Driving Description
EPHY
G Ground pin
Total: 196 pins
*NOTE:
1. IPD means internal pull-down; IPU means internal pull-up; P means power.
2. When SPI_CS1 acts as WATCH DOG RESET, a pull-high resistance is necessary.
DSRT5350_V1.0_112510
Form No.：QS-073-F02
Rev.：1
Kept by： DCC
-11-
Ret. Time： 5 Years
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet RT5350.PDF ] | |
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