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PDF QD14XL12 Data sheet ( Hoja de datos )
| Número de pieza | QD14XL12 | |
| Descripción | TFT LCD Module | |
| Fabricantes | Quanta | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de QD14XL12 (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
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Quanta Display Inc
Final
Specification
Quanta Display Inc.
SPECIFICATION
QD14XL1202 Page 1/26
Doc No. QD14XL1202
Doc. REV.: 00
Issue Date: 3/21/2005
RoHS compliant
Specification for TFT LCD Module
Model No.
QD14XL12 Rev.:02
? Approved By
Quanta Display Inc.
Andy Cheng
Mar. 21th 2005
Free Datasheet http://www.Datasheet4U.com
1 page  
Quanta Display Inc
QD14XL1202 Page 5/26
4. Input Terminals
4-1. TFT-LCD panel driving
CN1 ( 1 channel, LVDS signals – NSC/Ti standard and +3.3V DC power supply)
Using connector: FI-XB30S-HF10 (JAE)
Interface Cable Pin Assignments
PIN NO . SYMBOL
FUNCTION
1 VSS
Ground
2 VDD
Power Supply, 3.3 V (typical)
3 VDD
Power Supply, 3.3 V (typical)
4
V EEDID
DDC 3.3V power
5 NC
Reserved for supplier test point
6
Clk EEDID
DDC Clock
7
DATA EEDID
DDC Data
8 Rin0-
- LVDS differential data input (R0-R5, G0) (odd pixels)
9 Rin0+
+ LVDS differential data input (R0-R5, G0) (odd pixels)
10 VSS
Ground
11
Odd_Rin1-
- LVDS differential data input (G1-G5, B0-B1) (odd pixels)
12 Rin1+
+ LVDS differential data input (G1-G5, B0-B1) (odd pixels)
13 VSS
Ground
14 Rin2-
- LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
15 Rin2+
+ LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
16 VSS
Ground
17 ClkIN-
- LVDS differential clock input (odd pixels)
18 ClkIN+
+ LVDS differential clock input (odd pixels)
19 VSS
Ground
20 NC
No connect
21 NC
No connect
22 NC
No connect
23 NC
No connect
24 NC
No connect
25 NC
No connect
26 NC
No connect
27 NC
No connect
28 NC
No connect
29 NC
No connect
30 NC
No connect
? Note 1? Relation between LVDS signals and actual data shows below section (4-2).
? Note 2? The shielding case is connected with signal GND.
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5 Page 
Quanta Display Inc
7. Timing characteristics of LCD module input signals
7-1. Timing characteristics
(This is specified at digital outputs of LVDS driver.)
QD14XL1202 Page 11/26
Data
ENAB
Sync
CD
E
( Vertical)
Item( symbol)
Vsync cycle (TVA)
Blanking period(TVB)
Sync pulse width (TVC)
Back porch (TVD)
Sync pulse width + Back porch
(TVC+TVD)
Active display area (TVE)
Front porch (TVF)
A
Min.
-
803
35
4
0
35
768
0
Typ.
16.667
806
38
6
29
35
768
3
B
F
Max.
-
-
-
35
768
-
Unit Remark
ms Negative
line
line
line
line
line
line
line
(Horizontal)
Item( symbol)
Min.
Hsync cycle (THA)
19.2
1260
Blanking period (THB)
Sync pulse width (THC)
Back porch (THD)
Sync pulse width + Back
porch (THC +THD)
Active display area (THE)
Front porch (THF)
( Clock)
236
8
0
1500 - THA
1024
8
Typ.
20.677
1344
320
136
160
296
1024
24
Max.
-
1408
-
-
312
THA -
1024
1024
-
Unit
µs
clock
clock
clock
clock
clock
Remark
Negative
clock
clock
Item
Frequency
Min.
-
Typ.
65.0
Max.
67.0
Unit Remark
MHz ? Note1?
Note) In case of lower frequency, the deterioration of display quality, flicker etc., may be
occurred.
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11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet QD14XL12.PDF ] | |
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