PDF M514400D Data sheet ( Hoja de datos )

Número de pieza	M514400D
Descripción	MSM514400D
Fabricantes	OKI
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No Preview Available ! E2G0023-17-41 ¡ Semiconductor¡ Semiconductor This veMrsSioMn5:1J4a4n0. 01D99/8DL Previous version: May 1997 MSM514400D/DL 1,048,576-Word ¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM514400D/DL is a 1,048,576-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514400D/DL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM514400D/DL is available in a 26/20-pin plastic SOJ, 20- pin plastic ZIP, or 26/20-pin plastic TSOP. The MSM514400DL (the low-power version) is specially designed for lower-power applications. FEATURES • 1,048,576-word ¥ 4-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Package options: 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM514400D/DL-xxSJ) 20-pin 400 mil plastic ZIP (ZIP20-P-400-1.27) (Product : MSM514400D/DL-xxZS) 26/20-pin 300 mil plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product : MSM514400D/DL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM514400D/DL-50 MSM514400D/DL-60 MSM514400D/DL-70 Access Time (Max.) Cycle Time Power Dissipation tRAC tAA tCAC tOEA (Min.) Operating (Max.) Standby (Max.) 50 ns 25 ns 13 ns 13 ns 60 ns 30 ns 15 ns 15 ns 70 ns 35 ns 20 ns 20 ns 90 ns 110 ns 130 ns 550 mW 495 mW 440 mW 5.5 mW/ 1.1 mW (L-version) 1/17 Free Datasheet http://www.0PDF.com 1 page ¡ Semiconductor MSM514400D/DL DC Characteristics Parameter Symbol Condition Output High Voltage VOH IOH = –5.0 mA Output Low Voltage VOL IOL = 4.2 mA 0 V £ VI £ 6.5 V; Input Leakage Current ILI All other pins not under test = 0 V DQ disable Output Leakage Current ILO 0 V £ VO £ 5.5 V Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) RAS, CAS cycling, ICC1 tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable Average Power RAS cycling, Supply Current (CAS before RAS Refresh) ICC6 CAS before RAS Average Power RAS = VIL, Supply Current ICC7 CAS cycling, (Fast Page Mode) Average Power Supply Current tPC = Min. tRC = 125 ms, ICC10 CAS before RAS, (Battery Backup) tRAS £ 1 ms (VCC = 5 V ±10%, Ta = 0°C to 70°C) MSM514400 MSM514400 MSM514400 D/DL-50 D/DL-60 D/DL-70 Unit Note Min. Max. Min. Max. Min. Max. 2.4 VCC 2.4 VCC 2.4 VCC V 0 0.4 0 0.4 0 0.4 V –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 100 — 90 — 80 mA 1, 2 —2 —2— 2 mA 1 —1 —1— 1 — 200 — 200 — 200 mA 1, 5 — 100 — 90 — 80 mA 1, 2 — 5 — 5 — 5 mA 1 — 100 — 90 — 80 mA 1, 2 — 80 — 70 — 60 mA 1, 3 1, 4, — 300 — 300 — 300 mA 5 Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 4. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. 5. L-version. 5/17 Free Datasheet http://www.0PDF.com 5 Page ¡ Semiconductor MSM514400D/DL Fast Page Mode Read Cycle RAS VIH VIL – – CAS VIH VIL – – VIH – Address VIL – ,,,WE VIH VIL – – tAR tCRP tRCD tRAD tASR tRAH tASC tCAS tCSH tCAH Row Column tRCS tRASP tRHCP tPC tCP tCAS tRSH tCP tCAS tASC tCAH tRAL tASC tCAH Column tRCH tRCS tRCH Column tRCS tRP tCRP tRCH tAA tAA tAA tRRH tCPA tCPA OE VIH VIL – – DQ VOH – VOL – tOEA tCAC tRAC tOFF tOEZ Valid tCLZ Data-out tOEA tCAC tCLZ tOFF tOEZ Valid Data-out tOEA tCAC tCLZ tOFF tOEZ Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) RAS VIH VIL – – CASVIH– VIL – VIH – ,,,AddressVIL– tAR tCRP tRCD tCAS tASR tCSH tRAH tASC tCAH Row Column tRAD tCWL tRASP tPC tCP tCAS tASC tCAH Column tCWL tRHCP tRSH tCP tCAS tASC tCAHtRAL Column tRWL tRP tCRP WE VIH VIL – – tWCS tWCH tWP tWCR tWCS tWCH tWP tWCS tCWL tWCH tWP tDS tDH tDS tDH tDS tDH DQ VIH VIL – – Valid Data-in tDHR Valid Data-in Valid Data-in Note: OE = "H" or "L" "H" or "L" 11/17 Free Datasheet http://www.0PDF.com 11 Page

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