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PDF BD8381EFV-M Data sheet ( Hoja de datos )
| Número de pieza | BD8381EFV-M | |
| Descripción | LED Drivers | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Power Management ICs for Automotive Body Control
LED Drivers
for Automotive Light
BD8381EFV-M
No.11039ECT14
●Description
BD8381EFV-M is a white LED driver with the capability of withstanding high input voltage (50V MAX).
A current-mode buck-boost DC/DC controller is also integrated to achieve stable operation against voltage input and also to
remove the constraint of the number of LEDs in series connection.
The brightness can be controlled by either PWM or linear. The PWM brightness signal generation circuit is built into, and
the control without microcomputer is also possible.
●Features
1) Input voltage range 5.0 – 30 V
2) Integrated buck-boost current-mode DC/DC controller
3) Built-in CR timer for PWM brightness
4) PWM linear brightness
5) Built-in protection functions (UVLO, OVP, TSD, OCP, SCP)
6) LED error status detection function (OPEN/ SHORT)
7) HTSSOP-B28 package
●Applications
Headlight and running (DRL) of night of daylight, etc.
●Absolute maximum ratings (Ta=25℃)
Parameter
Symbol
Ratings
Unit
Power supply voltage
VCC
50
BOOT Voltage
VBOOT
55
SW,CS,OUTH Voltage
VSW, VCS, VOUTH
50
BOOT-SW Voltage
VBOOT-SW
7
VREG,OVP,OUTL,FAIL1,FAIL2,THM,SS,
COMP,RT,SYNC,EN,DISC,VTH,FB,LEDR,
LEDC,DRLIN, PWMOUT,CT Voltage
Power Consumption
VVREG,VOVP,VOUTL,VFAIL1,VFAIL2,VTHM,VSS,
VCOMP,VRT,VSYNCVEN,VDISC,VVTH,VFB,VLEDR,
VLEDC, ,VDRLIN,VPWMOUT VCT
Pd
-0.3～7 < VCC
1.45※1
Operating temperature range
Topr -40～+125
Storage temperature range
Tstg -55～+150
Junction temperature
Tjmax
150
※1 IC mounted on glass epoxy board measuring 70mm×70mm×1.6mm, power dissipated at a rate of 11.6mW/℃ at temperatures above 25℃.
※2 A radiation is not designed.
V
V
V
V
V
W
℃
℃
℃
●Operating conditions (Ta=25℃)
Parameter
Symbol
Ratings
Power supply voltage
VCC 5.0～30
Oscillating frequency range
External synchronization frequency range ※3 ※4
FOSC
FSYNC
200～600
fosc～600
External synchronization pulse duty range
FSDUTY
40～60
※3 Connect SYNC to GND or OPEN when not using external frequency synchronization.
※4 Do not switch between internal and external synchronization when an external synchronization signal is input to the device.
Unit
V
kHz
kHz
%
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
1/23
2012.06 - Rev.C
1 page  
BD8381EFV-M
●Block diagram and pin configuration
Technical Note
Vin VREG
FAIL1
VCC
VREG
UVLO TSD
OVP
OCP
OVP
CS
EN
SYNC
RT
COMP
VREG
SS
THM
DRLIN
VREG
DISC
VTH
PWM
Timer
Latch
Control Logic
OSC
SLOPE
PWM
OCP OVP
SS
ERR AMP
-
+
+
DRV
CTL
VREG
SHORT
Det
BOOT
OUTH
SW
DGND
OUTL
GND
LEDR
LEDC
PWMOUT
FB
CR
TIMER
OPEN/ SHORT/ SCP Detect
Timer
Latch
Open Det
SCP Det
FAIL2
PGND
CT
COUT
●Pin layout
BD8381EFV-M(HTSSOP-B28)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Fig.16
Fig.15 Buck-boost application composition
●Pin function table
Pin Symbol
Function
1 COMP Error amplifier output
2 SS Soft start
3
VCC
Input power supply
28
4 EN Enable input
5 RT Oscillation frequency-setting resistance input
27 6 SYNC External synchronization signal input
26
7
GND
Small-signal GND
25
8
THM
Thermally sensitive resistor connection pin
24 9 FB ERRAMP FB signal input pin
10
DISC
CR Timer discharge pin
23
11
VTH
CR Timer threshold pin
22 12 DRLIN DRL switch terminal (Pulse output setting terminal)
21
13
FAIL1
Failure signal output
20
14
FAIL2
LED open/short detection signal output
19
15
OVP
Over-voltage detection input
16
LEDC
LED short detection pin (LED detection side)
18
17
LEDR
LED short detection pin (Resistor detection side)
17 18 N.C.
-
16 19 PGND PWM brightness source pin
15 20 PWMOUT PWM brightness signal output pin
21 CT GND short protection timer setting pin
22
OUTL
Low-side external FET Gate Drive out put
23 DGND Low-side FET driver source pin
24 SW High-side FET Source pin
25 OUTH High-side external FET Gate Drive out put
26 CS DC/DC output current detection pin
27 BOOT High-side FET driver source pin
28 VREG Internal reference voltage output
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
5/23
2012.06 - Rev.C
5 Page 
BD8381EFV-M
Technical Note
●Error all condition
Protection
UVLO
Detecting Condition
[Detect]
VCC<4.3V
[Release]
VCC>4.5V
TSD
Tj>175℃
Tj<150℃
OVP
VOVP>2.0V
VOVP<1.45V
OCP
SCP
LED open
LED short
VCS≦VCC-0.6V
VFB<0.05V
(150ms delay when CT=0.1µF)
VFB<0.05V & VOVP>1.7V
lVLEDR-VLEDCl>0.2V
(100ms delay when FOSC=300kHz)
VCS>VCC-0.6V
EN or UVLO
EN or UVLO
EN or UVLO
Operation after detect
All blocks (but except REG)
shut down
All blocks (but except REG)
shut down
SS discharged
SS discharged
Counter starts and then latches off
all blocks (but except REG)
Counter starts and then latches off
all blocks (but except REG)
Counter starts and then latches off
all blocks (but except REG)
●Protection sequence
Vcc
EN
①
VREG
UVLO
THM
(Input by the
resistance division
of VREG. )
SYNC
DRLIN
SS
OUTL
VOUT
4.5V
Release
②
②
②
Fig.24
Power supply turning on sequence
① Please turn on EN with Vcc≧4.5V or more after impressing Vcc.
② Please fix the potential of DRLIN and THM before turning on EN.
③ A soft start operates at the same time as turning on EN, and the switching is output.
④ After turning on VCC, the order is not related to other input when inputting external PWM from VTH.）
※It leads to the destruction of IC and external parts because it doesn't error output according to an external constant of
adjacent pin 24pin SW terminal, 25pin OUTH terminal, 26pin CS terminal and 27pin BOOT terminal.
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
11/23
2012.06 - Rev.C
11 Page | ||
| Páginas | Total 24 Páginas | |
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