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PDF RDA1846 Data sheet ( Hoja de datos )
| Número de pieza | RDA1846 | |
| Descripción | Programming Guide | |
| Fabricantes | RDA | |
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RDA1846 Programming Guide
RDA1846
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
1
Free Datasheet http://www.Datasheet4U.com
1 page  
RDA1846
Doc. A: Interface
RDA1846 each register write is 24-bit long, including a r/ w bit,7-bit register address , and 16-bit data (MSB is
the first bit).
R/W
A[6:0]
D[15:0]
Note
If register address is more than 7FH, first write 0x0001 to 7FH, and then write value to the address
subtracted by 80H. Finally write 0x0000 to 7FH
Example: writing 85H register address is 0x001F .
Move 7FH 0x0001;
Move 05H 0x001F; 05H=85H-80H
Move 7FH 0x0000;
1. I2C Interface
RDA1846 enable software programming through I2C interface. Software controls chip working states, such as
Txon or Rxon operation, and reads status register to get operation result through I2C interface.
It includes two pins: SCLK and SDIO.
A I2C interface transfer begins with START condition, a command byte and data bytes, each byte has a
followed ACK (or NACK) bit, and ends with STOP condition. The command byte includes a 7-bit chip
address and a r/ w bit. The 7-bit chip address is 7’b0101110 when SEN is high, or is 7’1110001 when SEN is
low.The ACK ( or NACK) is always sent out by receiver. When in write transfer, data bytes is written out
from MCU, and when in read transfer, data bytes is read out from RDA1846.
Figure 1. I2C Interface Write Timing Diagram
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
5
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5 Page 
RDA1846
2bH[15:0]= xtal_freq<15:0>=12.8*1000=12800
2cH[12:0] =adclk_freq<15:0>=(12.8/2)*1000=6400
04H[0]= clk_mode =1
26M crystal (24MHz~28MHz)
2bH[15:0]= xtal_freq<15:0>=(26/2)*1000=13000
2cH[15:0] =adclk_freq<15:0>=(26/4)*1000=6500
04H[0]= clk_mode =0
4. Setting Tx and Rx
Bit
30H[13:12]
Name
channel_mode
30H[6]
30H[5]
tx_on
rx_on
Function
11 = 25khz channel mode
00 = 12.5khz channel mode
10,01=reserved
1 = on
0 = off
1 = on
0 = off
5. Deep sleep
Bit
30H[2]
Name
pdn_reg
Function
The same as pdn pin
1 = enable
0 = disable
While Normal mode, pdn_reg and PDN pin must be high at the same time. Only one of pdn_reg and PDN pin
is low ,which can turn into deep sleep.
6. TX voice channel
Bit Name
3cH[15:14] voice_sel<1:0>
Function
=00; Tx voice signal from MIC
=01; Tx inner sine tone setted by tone2
=10; Tx code from GPIO1 code_in (gpio1<1:0> must be
set to 01)
=11; not Tx any signal
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
10
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11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet RDA1846.PDF ] | |
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