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PDF CAT7581 Data sheet ( Hoja de datos )
| Número de pieza | CAT7581 | |
| Descripción | Synchronous Single Buck PWM Controller | |
| Fabricantes | CAT | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CAT7581 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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CAT7581
Synchronous Single Buck PWM Controller
Confidentiality Statement:
This Data Sheet (including any attachments) is for the sole use of the intended
recipient(s) and contains confidential, proprietary and privileged information. Any
unauthorized review, use, disclosure or distribution is prohibited. If you are not the
intended recipient, please immediately destroy all copies of the original message.
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1 page  
Synchronous Single Buck PWM Controller
CAT7581
Absolute Maximum Ratings (Note 1)
Supply Voltage, VCC………………………………………..…….15V
Boot Voltage, VBOOT……………….………….15V wrt/PHASE
High Side Driver Output……….…….…….15V wrt/PHASE
Low Side Driver Output………...………………………….…….15V
Feedback………...………………………….……………………………5.5V
COMP………...………………………….…………………………………5.5V
ESD Classification (Note 2) …...…….…………………Class 2
Junction Temperature………...…...…….……………………150°C
Storage Temperature Range.............-65oC to 150°C
Lead Temperature (Soldering 10s)…………...260°C
Recommended Operating Conditions
Supply Voltage, VCC……………………………..…+12V ±10%
Ambient Temperature Range………………-30°C to 85°C
Thermal Resistance
θJA
SOP8 Package………… …91
θJC
43 ( °C/W )
Electrical Characteristic:
(Recommended Operating Conditions, Unless Otherwise Noted; VCC = 12V; Temperature = 0 - 70 oC (typical = 25 oC))
Parameter
Supply Voltage
Input Voltage Range
Supply Current
VCC Nominal Supply Current
VCC Undervoltage Lockout
UVLO Threshold
UVLO Hysteresis
Switching Regulator
Reference Voltage
Oscillator Frequency
Ramp-Amplitude Voltage
Minimum Duty Cycle
ERROR Amplifier
Open Loop DC Gain
Transconductance
FB Bias Current
Gate Driver
UGATE Sink (Note 3)
UGATE Source (Note 3)
LGATE Sink (Note 3)
LGATE Source (Note 3)
Internal Soft-Start
Time
VOUT Under voltage Protection
UVP Level
VOUT Over voltage Protection
OVP Level
Over Current Protection
OC Current Source
Disable
OCSET Disable Threshold
OCSET Disable Hysteresis
Test Conditions
Ugate & Lgate Open
VCC rising Edge
TA = 0℃ to 70℃
VFB=1V
VBOOT-VPHASE=12V;VUGATE-VPHASE =1V
VBOOT-VPHASE=12V;VUGATE-VPHASE =6V
Vcc=12V;VLGATE=1V
Vcc=12V;VLGATE=6V
Switching frequency = 300 Khz
Percent of Nominal
Percent of Nominal
Min Typ. Max
4.5 13.2
2
3.85 4.2
0.5
0.784 0.800 0.816
250 300 350
1.5
0
90
7.5
0.1
2.5 5
0.8 1.4
1.4 3
0.5 0.8
2048
64 67 70
115 118 121
35 40 45
0.15
40
Unit
V
mA
V
V
V
KHz
V
%
dB
μS
μA
Ω
A
Ω
A
cycle
%
%
μA
V
mV
Note:
1. Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Devices are ESD sensitive. Handling precaution recommended.
3. Guaranteed by design; not production tested.
The CAT logo is a registered trademark of Chip Advanced Technology
2008 Chip Advanced Technology Inc. – All Right Reserved.
Apr-2008 Rev:1.3 5/16
Free Datasheet http://www.datasheetlist.com/
5 Page 
Synchronous Single Buck PWM Controller
CAT7581
sheet and a calculation can be made to determine
the IC junction temperature. In addition, a thermal
resistance (Junction − to − Ambient / Safe
Operating Area) curve has been included below to
further aid design. However, it should be noted that
the physical layout of the board, the proximity of
other heat sources such as MOSFETs and
inductors, and the amount of metal connected to the
IC, impact the temperature of the device. Use these
calculations as a guide, but measurements should
be taken in the actual application.
PUPPER
=
Io 2
* RDS (ON )
*D+
1
2
IO
*VIN
* tSW
* FS
PLOWER = Io 2 * RDS (ON ) * (1 − D)
Where,
D is the duty cycle = VOUT .
VIN
tSW is the switching interval.
Fs is the switching frequency.
POWER MOS SELECTION
CAT7581 requires 2 N-channel POWER MOSs for
each PWM output. These should be selected base
on RDS (ON ) , gate supply voltage, gate charge
(capacitance) and thermal management
requirements. In general, the upper power MOS
should be chosen to minimize the gate charge,
since switching loses dominate. Since the lower
power MOS is on most of the time, low
RDS (ON ) should be the main consideration.
It can be advantageous to use multiple POWER
MOSs to reduce power consumption. By placing a
number of MOSs in parallel, the effective RDS (ON )
is reduced, thus reducing the Ohmic power loss.
However, placing MOSs in parallel increases the
gate capacitance so that switching losses increase.
As long as adding another parallel MOS reduces
the Ohmic power loss more than the switching
losses increase, there is some advantage to doing
so.
The following equations can be used to calculate
power dissipation in the power MOSs
The CAT logo is a registered trademark of Chip Advanced Technology
2008 Chip Advanced Technology Inc. – All Right Reserved.
Apr-2008 Rev:1.3 11/16
Free Datasheet http://www.datasheetlist.com/
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CAT7581.PDF ] | |
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