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PDF SDIN5D2-2G-L Data sheet ( Hoja de datos )

Número de pieza SDIN5D2-2G-L
Descripción iNAND e.MMC 4.41 I/F
Fabricantes Sandisk 
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e.MMC 4.41 I/F
Preliminary Data Sheet
80-36-03433
February 2010
SanDisk Corporation
Corporate Headquarters • 601 McCarthy Boulevard • Milpitas, CA 95035
Phone (408) 801-1000 • Fax (408) 801-8657
www.sandisk.com
Free Datasheet http://www.datasheet-pdf.com/

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SDIN5D2-2G-L pdf
80-36-03433
Introduction
SanDisk iNAND e.MMC 4.41 I/F - data Sheet
1. INTRODUCTION
1.1. General Description
iNAND is an Embedded Flash Drive (EFD) designed for mobile handsets and consumer electronic
devices. iNAND is a hybrid device combining an embedded thin flash controller and standard MLC
NAND flash memory, with an industry standard e.MMC 4.411 interface.
Empowered with a new e.MMC4.41 feature set such as Boot and RPMB partitions, HPI,
Background Operations and HW Reset the iNAND e.MMC is the optimal device for reliable code
and data storage.
Designed specifically for mobile multimedia applications, iNAND is the most mature on board
SD/MMC device since 2005, providing mass storage of up to 32GB in JEDEC compatible form
factors, with low power consumption and high performance - an ideal solution for multimedia
handsets of 2.5G, 3G, 3.5G and 4G.
In addition to the high reliability and high system performance offered by the current iNAND
family of products, iNAND offers plug-and-play integration and support for multiple NAND
technology transitions, as well as features such as advanced power management scheme.
iNAND uses advanced Multi-Level Cell (MLC) NAND flash technology, enhanced by SanDisk’s
embedded flash management software running as firmware on the flash controller.
iNAND architecture and embedded firmware fully emulates a hard disk to the host processor,
enabling read/write operations that are identical to a standard, sector-based hard drive. In addition,
SanDisk firmware employs patented methods, such as virtual mapping, dynamic and static wear-
leveling, and automatic block management to ensure high data reliability and maximize flash life
expectancy.
SanDisk iNAND provides up to 32GB of memory for use in mass storage applications. In addition
to the mass-storage-specific flash memory chip, iNAND includes an intelligent controller, which
manages interface protocols, data storage and retrieval, error correction code (ECC) algorithms,
defect handling and diagnostics, power management and clock control.
Figure 1 shows a block diagram of the SanDisk iNAND with MMC Interface.
iNAND enables multimedia driven applications such as music, photo, video, TV, GPS, games,
email, office and other applications.
The breakthrough in performance and design makes iNAND the ideal solution for mobile handset
vendors, portable navigation and Automotive Infotainment vendors who require easy integration,
fast time to market and high-capacity.
1.2. Plug-and-Play Integration
iNAND optimized architecture eliminates the need for complicated software integration and testing
processes and enables a practically plug-and-play integration in the system. The replacement of one
iNAND device with another of a newer generation requires virtually no changes to the host. This
makes iNAND the perfect solution for platforms and reference designs, as it allows for the
1 Compatible to JESD84-A441
80-36-03433
Free Datasheet http://www.datasheet-pdf.com/

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SDIN5D2-2G-L arduino
80-36-03433
e.MMC4.41 Features Overview
SanDisk iNAND e.MMC 4.41 I/F -Data Sheet
2.9. Enhanced Write Protection
To allow the host to protect data against erase or write, the iNAND supports two levels of write
protect command10:
The entire iNAND (including the Boot Area Partitions, General Purpose Area Partition, and
User/Enhanced User Data Area Partition) may be write-protected by setting the permanent
or temporary write protect bits in the CSD.
Specific segments of the iNAND may be permanently, power-on or temporarily write
protected. Segment size can be programmed via the EXT_CSD register.
For additional information please refer JESD84-A441 standard.
2.10. High Priority Interrupt (HPI)
Many operating-systems use demand-paging to launch a process requested by the user. If the host
needs to fetch pages while in a middle of a wrie operation, the request will be delayed until the
completion of the write command which, in the worst case scenario, can take up to 350ms.
The high priority interrupt (HPI) as defined in JESD84-A441 enables low read latency operation
by suspending a lower priority operation before it is actually completed. This mechanism can
reduce read latency, in typical condition, to 5msec.
For additional information on the HPI function, refer to JESD84-A441 standard section 7.6.20
2.11. Background Operations
Devices have various maintenance operations that they need to perform internally, such as garbage
collection, erase and compaction. In order to reduce latencies during time critical operations, it is
better to execute maintenance operations when the device is not serving the host.
Operations are then separated into two types: foreground operations – such as read or write
commands, and background operations – operations that the device can execute when the host is
not being served.
For additional information on Background Operations, refer to JESD84-A441 standard section
7.6.19
2.12. H/W Reset
Hardware reset may be used by host to reset the device, moving the card to a Pre-idle state and
disabling the power-on period write protect on blocks that was set as power-on write protect before
the reset was asserted. For more information, refer to JESD84-A441 standard.
2.13. DDR I/F
Support DDR signaling to double bus performance. For additional information please refer to
JESD84-A441 standard.
10 For additional information refer to JEDEC Standards No. JESD84-A441
© 2010 SanDisk Corporation
80-36-03433
Free Datasheet http://www.datasheet-pdf.com/

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