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PDF UCC3583 Data sheet ( Hoja de datos )

Número de pieza UCC3583
Descripción (UCC1583 - UCC3583) Switch Mode Secondary Side Post Regulator
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Switch Mode Secondary Side Post Regulator
UCC1583
UCC2583
UCC3583
FEATURES
Precision Secondary Side Post
Regulation for Multiple Output Power
Supplies
Useful for Both Single Ended and
Center Tapped Secondary Circuits
Ideal Replacement for Complex
Magnetic Amplifier Regulated Circuits
Leading Edge Modulation
Does Not Require Gate Drive
Transformer
High Frequency (>500kHz) Operation
Applicable for Wide Range of Output
Voltages
High Current Gate Driver (0.5A
Sink/1.5A Source)
Average Current Limiting Loop
DESCRIPTION
The UCC3583 is a synchronizable secondary side post regulator for preci-
sion regulation of the auxiliary outputs of multiple output power supplies. It
contains a leading edge pulse width modulator, which generates the gate
drive signal for a FET power switch connected in series with the rectifying
diode. The turn-on of the power switch is delayed from the leading edge of
the secondary power pulse to regulate the output voltage. The UCC3583
contains a ramp generator slaved to the secondary power pulse, a voltage
error amplifier, a current error amplifier, a PWM comparator and associ-
ated logic, a gate driver, a precision reference, and protection circuitry.
The ramp discharge and termination of the gate drive signal are triggered
by the synchronization pulse, typically derived from the falling edge of the
transformer secondary voltage. The ramp starts charging again once its
low threshold is reached. The gate drive signal is turned on when the ramp
voltage exceeds the control voltage. This leading edge modulation tech-
nique prevents instability when the UCC3583 is used in peak current mode
primary controlled systems.
The controller operates from a floating power supply referenced to the out-
put voltage being controlled. It features an undervoltage lockout (UVLO)
circuit, a soft start circuit, and an averaging current limit amplifier. The cur-
rent limit can be programmed to be proportional to the output voltage, thus
achieving foldback operation to minimize the dissipation under short circuit
conditions.
(continued)
TYPICAL APPLICATION AND BLOCK DIAGRAM
Note: Pin connections shown for 14-pin packages.
11/98
UDG-96201-2
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UCC3583 pdf
APPLICATION INFORMATION (cont.)
For the circuit shown in Figure 5a, CC1 is charged when
the transformer voltage is positive and the synchronous
switch is on. During the off period of Q-SYNC, the charge
is transferred to CC2 through diode DC2. Diode DC3
charges CC2 during the blocking interval of Q-SYNC.
This method is preferable when the transformer positive
voltage is high enough to generate the required bias volt-
age. For the circuit shown in Figure 5b, CC1 is charged
during the period when reverse (reset) voltage appears
across the secondary. The charge on CC1 is transferred
to CC2 through DC2 when Q-SYNC turns on. This
method is preferable when the reverse voltage is high
enough to generate the required bias voltage. The series
resistor should be chosen to handle the required voltage
drop at full IC operating current when the zener clamp
across VDD and COM is activated.
The following is a description of the major functional
blocks of the UCC3583. Refer to Figure 6 (Typical Appli-
cation Circuit) for component designations.
UVLO and Start Up
The UCC3583 has an internal undervoltage lockout cir-
cuit which keeps the internal circuitry inactive until VDD
exceeds the upper threshold (9V). Once the chip is acti-
vated, VDD has to be above the lower UVLO threshold
(8.4V) for it to remain functional. The IC requires a low
startup current of only 100µA when VDD is under the
UVLO threshold. VDD has an internal clamp of 14V
which can sink up to 10mA. Measures must be taken not
to exceed this current. The internal reference (REF) is
brought up when the UVLO on threshold is exceeded.
The soft start pin provides an effective means to start the
IC in a controlled manner. An internal current of 10µA
starts discharging a capacitor connected to SS when the
UVLO conditions have been removed. The voltage on
SS controls the duty cycle of the output during the dis-
charge period.
Synchronizing Circuit and Oscillator
UCC3583 is primarily intended for synchronizable opera-
tion where its switching frequency is determined by the
secondary pulse of the power transformer. However, it
has an internal oscillator which allows it to operate in
free-running mode when an external synchronization
pulse is not available. The switching frequency is deter-
mined by resistor RT connected between REF and
RAMP and capacitor CT connected from RAMP to GND.
The frequency is given by:
= CH + DIS
and
CH = • T T
UCC1583
UCC2583
UCC3583
T RAMP (p` p)
DIS =
RAMP (dis)
T
The values of RT and CT are also dictated by the fact
that the ramp is discharged through an internal imped-
ance of 2k. The value of RT needs to be at least 50k to
ensure that the internal discharge current is the current
through RT during the entire discharge period. This re-
sults in making the value of CT relatively small for a de-
sired frequency of operation.
When the synchronizing signal is available, the oscillator
frequency should be programmed to be lower than the
synchronizing frequency to ensure proper operation. A
large difference in self-running and synchronizing fre-
quencies leads to smaller ramp amplitude and higher
noise sensitivity. The ramp capacitor is discharged when
the synchronization signal arrives and begins charging
when the low threshold is crossed.
There are two methods to synchronize to the secondary
pulse. One method is to use the rising edge of the sec-
ondary pulse, which reduces the maximum duty cycle
available. Subsequently, the post regulator switch cannot
be turned on during the CT discharge time. The other
method is to use the falling edge of the secondary pulse
for synchronization. This method is preferable because it
allows a slower discharge of the ramp capacitor without
affecting the maximum available duty cycle of the post
regulator. The UCC3583 SYNC input needs to reach a
fixed threshold (1.0V typical) for synchronization to take
effect. Hence the IC is usable with either method of syn-
chronization. However, the UCC3583 oscillator configu-
ration is better suited for synchronization to the falling
edge. A recommended method to implement the syn-
chronization is shown in Figure 6. By connecting SYNC
to a resistive divider between REF and the secondary
terminal S2, the synchronization is achieved whenever
the voltage on S2 goes from a negative value to zero. RA
and RB should be selected so that the voltage on the
SYNC pin varies from 0V to 1V. Placement of a Schottky
diode from SYNC to COM prevents the voltage at SYNC
from going negative. The internal hysteretic SYNC com-
parator has an inverting input set to 0.5V with about
±0.5V hysteresis.
PWM Comparator
The UCC3583 uses a leading edge PWM scheme. In a
leading edge PWM, the output pulse (gate signal) is
turned on when the error amplifier crosses the PWM
ramp and turned off by the clock/oscillator. Leading edge
modulation is naturally provided by magamp type post
regulators and is an essential feature for post regulators.
Without the leading edge modulation in a multiple output
5
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