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PDF IDT72275 Data sheet ( Hoja de datos )
| Número de pieza | IDT72275 | |
| Descripción | (IDT72275 / IDT72285) CMOS SUPERSYNC FIFO | |
| Fabricantes | IDT | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IDT72275 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
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CMOS SUPERSYNC FIFO™
32,768 x 18
65,536 x 18
PRELIMINARY
IDT72275
IDT72285
Integrated Device Technology, Inc.
FEATURES:
• Choose among the following memory organizations:
IDT72275
32,768 x 18
IDT72285
65,536 x 18
• Pin-compatible with the IDT72255LA/72265LA SuperSync
FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each
flag can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and
writing simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the
64-pin Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
DESCRIPTION:
The IDT72275/72285 are exceptionally deep, high speed,
CMOS First-In-First-Out (FIFO) memories with clocked read
and write controls. These FIFOs offer numerous improve-
ments over previous SuperSync FIFOs, including the following:
• The limitation of the frequency of one clock input with
respect to the other has been removed. The Frequency
Select pin (FS) has been removed, thus it is no longer
necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed
and short.
• The first word data latency period, from the time the first
word is written to an empty FIFO to the time it can be read,
is now fixed and short. (The variable clock cycle counting
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0 -D17
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
32,768 x 18
65,536 x 18
RESET
LOGIC
OUTPUT REGISTER
FLAG
LOGIC
READ POINTER
FWFT/SI
READ
CONTROL
LOGIC
RCLK
Q0 -Q17
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1998 Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
4674 drw 01
SEPTEMBER 1998
DSC-4674/-
1
Free Datasheet http://www.datasheet-pdf.com/
1 page  
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
Symbol
VTERM
TSTG
IOUT
Rating
Terminal Voltage
with respect to GND
Storage
Temperature
DC Output Current
Commercial
–0.5 to +7
–55 to +125
–50 to +50
Unit
V
°C
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
Symbol
Parameter
VCC Supply Voltage
GND Supply Voltage
Min.
4.5
0
Typ.
5.0
0
Max.
5.5
0
VIH
VIL(1)
Input High Voltage
Input Low Voltage
2.0 —
——
—
0.8
TA Operating Temperature 0 — 70
Commercial
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
Unit
V
V
V
V
°C
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
IDT72275
IDT72285
Commercial
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
Max.
Unit
ILI(1)
ILO(2)
Input Leakage Current
Output Leakage Current
–1 1 µA
–10 10 µA
VOH Output Logic “1” Voltage, IOH = –2 mA
2.4 — V
VOL Output Logic “0” Voltage, IOL = 8 mA
— 0.4 V
ICC1(3,4,5) Active Power Supply Current
— 90 mA
ICC2(3,6)
Standby Current
— 20 mA
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 20 + 1.8*fS + 0.02*CL*fS (in mA) with VCC = 5V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels),
data switching at fS/2, CL = capacitive load (in pF).
6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions
Max.
CIN(2)
COUT(1,2)
Input
Capacitance
Output
Capacitance
VIN = 0V
VOUT = 0V
10
10
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
Unit
pF
pF
5
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5 Page 
IDT72275/72285 SUPERSYNC FIFO™
32,768 x 18, 65,536 x 18
COMMERCIAL TEMPERATURE RANGE
change in level will only be noticeable if EF was HIGH before
setup. During this period, the internal read pointer is initialized
to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and
read operations may begin starting with the first location in
memory. Since IDT Standard mode is selected, every word
read including the first word following Retransmit setup re-
quires a LOW on REN to enable the rising edge of RCLK. See
Figure 11, Retransmit Timing (IDT Standard Mode), for the
relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning
of the Retransmit setup by setting OR HIGH. During this
period, the internal read pointer is set to the first location of the
RAM array.
When OR goes LOW, Retransmit setup is complete; at the
same time, the contents of the first location appear on the
outputs. Since FWFT mode is selected, the first word
appears on the outputs, no LOW on REN is necessary.
Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit
Timing (FWFT Mode), for the relevant timing diagram.
For either IDT Standard mode or FWFT mode, updating
of the PAE , HF and PAF flags begin with the rising edge of
RCLK that RT is setup. PAE is synchronized to RCLK, thus
on the second rising edge of RCLK after RT is setup, the PAE
flag will be updated. HF is asynchronous, thus the rising
edge of RCLK that RT is setup will update HF . PAF is
synchronized to WCLK, thus the second rising edge of
WCLK that occurs tSKEW after the rising edge of RCLK that
RT is setup will update PAF . RT is synchronized to RCLK.
11
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11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet IDT72275.PDF ] | |
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