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PDF M45PE40 Data sheet ( Hoja de datos )
| Número de pieza | M45PE40 | |
| Descripción | Page-Erasable Serial Flash Memory | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M45PE40
4 Mbit, Low Voltage, Page-Erasable Serial Flash Memory
With Byte-Alterability and a 25 MHz SPI Bus Interface
FEATURES SUMMARY
■ 4Mbit of Page-Erasable Flash Memory
■ Page Write (up to 256 Bytes) in 11ms (typical)
■ Page Program (up to 256 Bytes) in 1.2ms
(typical)
■ Page Erase (256 Bytes) in 10ms (typical)
■ Sector Erase (512 Kbit)
■ 2.7 to 3.6V Single Supply Voltage
■ SPI Bus Compatible Serial Interface
■ 25MHz Clock Rate (maximum)
■ Deep Power-down Mode 1µA (typical)
■ Electronic Signature
– JEDEC Standard Two-Byte Signature
(4013h)
■ More than 100000 Write Cycles
■ More than 20 Year Data Retention
Figure 1. Packages
VDFPN8 (MP)
6x5mm (MLP8)
8
1
SO8W (MW)
208 mils width
January 2005
1/36
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1 page  
M45PE40
SUMMARY DESCRIPTION
The M45PE40 is a 4Mbit (512K x 8 bit) Serial
Paged Flash Memory accessed by a high speed
SPI-compatible bus.
The memory can be written or programmed 1 to
256 bytes at a time, using the Page Write or Page
Program instruction. The Page Write instruction
consists of an integrated Page Erase cycle fol-
lowed by a Page Program cycle.
The memory is organized as 8 sectors, each con-
taining 256 pages. Each page is 256 bytes wide.
Thus, the whole memory can be viewed as con-
sisting of 2048 pages, or 524288 bytes.
The memory can be erased a page at a time, using
the Page Erase instruction, or a sector at a time,
using the Sector Erase instruction.
Figure 2. Logic Diagram
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
Reset
Reset
VCC Supply Voltage
VSS Ground
Figure 3. VDFPN and SO Connections
D
C
S
W
Reset
VCC
M45PE40
Q
M45PE40
D
C
Reset
S
1
2
3
4
8Q
7 VSS
6 VCC
5W
AI04041D
VSS
AI04040C
Note: 1. There is an exposed die paddle on the underside of the
MLP8 package. This is pulled, internally, to VSS, and
must not be allowed to be connected to any other voltage
or signal line on the PCB.
2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
5/36
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5 Page 
Figure 6. Block Diagram
Reset
W
S
C
D
Q
Control Logic
Address Register
and Counter
M45PE40
High Voltage
Generator
I/O Shift Register
256 Byte
Data Buffer
Status
Register
7FFFFh
10000h
00000h
256 Bytes (Page Size)
X Decoder
000FFh
First 256 Pages can
be made read-only
AI04042B
11/36
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11 Page | ||
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