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PDF M45PE40 Data sheet ( Hoja de datos )
| Número de pieza | M45PE40 | |
| Descripción | NOR Flash Memory | |
| Fabricantes | Micron | |
| Logotipo |  |
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75MHz, Serial Peripheral Interface Flash Memory
Features
Micron Serial NOR Flash Memory
3V, 4Mb Page Erasable with Byte Alterability
M45PE40
Features
• SPI bus-compatible serial interface
• 75 MHz clock frequency (MAX)
• 2.7–3.6V single supply voltage
• 4Mb of page-erasable Flash memory
• Page size: 256 bytes
– Page write: 11ms (TYP)
– Page program: 0.8ms (TYP)
– Page erase: 10ms (TYP)
• Sector erase: 64KB
• Hardware write protection of the bottom memory
area 64KB
• Electronic signature
– JEDEC-standard, 2-byte signature (4013h)
• Deep power-down mode: 1µA (TYP)
• WRITE cycles per sector: >100,000
• Years of data retention: >20
• Packages (RoHS-compliant)
– VFQFPN8 (MP) 6mm x 5mm
– SO8W (MW) 208 mil
– SO8N (MN) 150 mil
PDF: 09005aef845660fc
m45pe40.pdf - Rev. B 06/13 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Free Datasheet http://www.Datasheet-PDF.com/
1 page  
75MHz, Serial Peripheral Interface Flash Memory
Functional Description
Functional Description
The M45PE40 is a 4Mb (512Kb x 8) serial Flash memory device accessed by a high-
speed, SPI-compatible bus.
The memory can be written or programmed 1 to 256 bytes at a time using the PAGE
WRITE or PAGE PROGRAM command. The PAGE WRITE command consists of an inte-
grated PAGE ERASE cycle followed by a PAGE PROGRAM cycle.
The memory is organized as 8 sectors, each containing 256 pages. Each page is 256
bytes wide. The entire memory can be viewed as consisting of 2048 pages, or 524,288
bytes.
The memory can be erased one page at a time using the PAGE ERASE command or one
sector at a time using the SECTOR ERASE command.
Figure 1: Logic Diagram
VCC
DQ0
C
S#
W#
RESET#
DQ1
Table 1: Signal Names
Signal Name
C
DQ0
DQ1
S#
W#
RESET#
VCC
VSS
Function
Serial clock
Serial data input
Serial data output
Chip select
Write protect
Reset
Supply voltage
Ground
VSS
Direction
Input
Input
Output
Input
Input
Input
–
–
PDF: 09005aef845660fc
m45pe40.pdf - Rev. B 06/13 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Free Datasheet http://www.Datasheet-PDF.com/
5 Page 
75MHz, Serial Peripheral Interface Flash Memory
Operating Features Overview
Polling During a WRITE, PROGRAM, or ERASE Cycle
The following commands can be completed faster by not waiting for the worst-case de-
lay (tW, tPP, tPE, tBE, or tSE).
The write in progress (WIP) bit is provided in the status register so that the application
program can monitor this bit in the status register, polling it to establish when the pre-
vious WRITE, PROGRAM, or ERASE cycle is complete.
Reset
An internal power-on reset circuit helps protect against inadvertent data writes. Addi-
tional protection is provided by driving RESET# LOW during the power-on process, and
driving it HIGH only when VCC has reached the correct voltage level, VCC,min.
Active Power, Standby Power, and Deep Power-Down
When chip select (S#) is LOW, the device is selected and in the active power mode.
When S# is HIGH, the device is deselected, but could remain in the active power mode
until all internal cycles have completed (PROGRAM, ERASE, WRITE). The device then
goes in to the standby power mode, and power consumption drops to ICC1.
The deep power-down mode is entered when the DEEP POWER-DOWN command is
executed. The device power consumption drops further to ICC2. The device remains in
this mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While
in the deep power-down mode, the device ignores all WRITE, PROGRAM, and ERASE
commands. This provides an extra software protection mechanism when the device is
not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or
ERASE operations. For further information, see the DEEP POWER-DOWN section.
Status Register
The status register contains a number of status bits that can be read by the READ STA-
TUS REGISTER (RDSR) command. For a detailed description of the status register bits,
see the READ STATUS REGISTER section.
Protection Modes
Nonvolatile memory is used in environments that can include excessive noise. The fol-
lowing capabilities help protect data in these noisy environments.
Power-on reset and an internal timer (tPUW) can provide protection against inadver-
tent changes while the power supply is outside the operating specification.
WRITE, PROGRAM, and ERASE commands are checked before they are accepted for ex-
ecution to ensure they consist of a number of clock pulses that is a multiple of eight.
All commands that modify data must be preceded by a WRITE ENABLE command to set
the write enable latch (WEL) bit. This bit is returned to its reset state by the following
events.
• Power-up
• Reset (RESET#) driven LOW
• WRITE DISABLE command completion
• PAGE WRITE command completion
• PAGE PROGRAM command completion
PDF: 09005aef845660fc
m45pe40.pdf - Rev. B 06/13 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Free Datasheet http://www.Datasheet-PDF.com/
11 Page | ||
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| PDF Descargar | [ Datasheet M45PE40.PDF ] | |
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