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Número de pieza 82801GHM
Descripción I/O Controller Hub 7
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Intel® I/O Controller Hub 7 (ICH7)
Family
Datasheet
— For the Intel® 82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH,
82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U I/O
Controller Hubs
April 2007
Document Number: 307013-003
Free Datasheet http://www.datasheet4u.net/

1 page




82801GHM pdf
5.6
5.7
5.8
5.9
5.10
DMA Operation (D31:F0) .................................................................................. 124
5.6.1 Channel Priority ................................................................................... 124
5.6.1.1 Fixed Priority.......................................................................... 125
5.6.1.2 Rotating Priority ..................................................................... 125
5.6.2 Address Compatibility Mode ................................................................... 125
5.6.3 Summary of DMA Transfer Sizes ............................................................. 125
5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count by
Words ................................................................................... 126
5.6.4 Autoinitialize........................................................................................ 126
5.6.5 Software Commands............................................................................. 126
LPC DMA (Desktop and Mobile Only) .................................................................. 127
5.7.1 Asserting DMA Requests ........................................................................ 127
5.7.2 Abandoning DMA Requests .................................................................... 127
5.7.3 General Flow of DMA Transfers ............................................................... 128
5.7.4 Terminal Count .................................................................................... 128
5.7.5 Verify Mode ......................................................................................... 128
5.7.6 DMA Request Deassertion...................................................................... 129
5.7.7 SYNC Field / LDRQ# Rules ..................................................................... 129
8254 Timers (D31:F0) ..................................................................................... 130
5.8.1 Timer Programming .............................................................................. 131
5.8.2 Reading from the Interval Timer............................................................. 132
5.8.2.1 Simple Read........................................................................... 132
5.8.2.2 Counter Latch Command.......................................................... 132
5.8.2.3 Read Back Command .............................................................. 132
8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 133
5.9.1 Interrupt Handling ................................................................................ 134
5.9.1.1 Generating Interrupts .............................................................. 134
5.9.1.2 Acknowledging Interrupts ........................................................ 134
5.9.1.3 Hardware/Software Interrupt Sequence ..................................... 135
5.9.2 Initialization Command Words (ICWx) ..................................................... 135
5.9.2.1 ICW1 .................................................................................... 135
5.9.2.2 ICW2 .................................................................................... 136
5.9.2.3 ICW3 .................................................................................... 136
5.9.2.4 ICW4 .................................................................................... 136
5.9.3 Operation Command Words (OCW) ......................................................... 136
5.9.4 Modes of Operation .............................................................................. 136
5.9.4.1 Fully Nested Mode................................................................... 136
5.9.4.2 Special Fully-Nested Mode........................................................ 137
5.9.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 137
5.9.4.4 Specific Rotation Mode (Specific Priority).................................... 137
5.9.4.5 Poll Mode ............................................................................... 137
5.9.4.6 Cascade Mode ........................................................................ 138
5.9.4.7 Edge and Level Triggered Mode................................................. 138
5.9.4.8 End of Interrupt (EOI) Operations ............................................. 138
5.9.4.9 Normal End of Interrupt........................................................... 138
5.9.4.10 Automatic End of Interrupt Mode .............................................. 138
5.9.5 Masking Interrupts ............................................................................... 139
5.9.5.1 Masking on an Individual Interrupt Request ................................ 139
5.9.5.2 Special Mask Mode .................................................................. 139
5.9.6 Steering PCI Interrupts ......................................................................... 139
Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 140
5.10.1 Interrupt Handling ................................................................................ 140
5.10.2 Interrupt Mapping ................................................................................ 140
5.10.3 PCI / PCI Express* Message-Based Interrupts .......................................... 141
5.10.4 Front Side Bus Interrupt Delivery ........................................................... 141
5.10.4.1 Edge-Triggered Operation......................................................... 142
Intel ® ICH7 Family Datasheet
5
Free Datasheet http://www.datasheet4u.net/

5 Page





82801GHM arduino
7.1.40 TCTL—TCO Configuration Register........................................................... 282
7.1.41 D31IP—Device 31 Interrupt Pin Register.................................................. 283
7.1.42 D30IP—Device 30 Interrupt Pin Register.................................................. 284
7.1.43 D29IP—Device 29 Interrupt Pin Register.................................................. 285
7.1.44 D28IP—Device 28 Interrupt Pin Register (Desktop and Mobile Only) ............ 286
7.1.45 D27IP—Device 27 Interrupt Pin Register.................................................. 287
7.1.46 D31IR—Device 31 Interrupt Route Register.............................................. 287
7.1.47 D30IR—Device 30 Interrupt Route Register.............................................. 289
7.1.48 D29IR—Device 29 Interrupt Route Register.............................................. 290
7.1.49 D28IR—Device 28 Interrupt Route Register.............................................. 292
7.1.50 D27IR—Device 27 Interrupt Route Register.............................................. 293
7.1.51 OIC—Other Interrupt Control Register ..................................................... 294
7.1.52 RC—RTC Configuration Register.............................................................. 295
7.1.53 HPTC—High Precision Timer Configuration Register ................................... 295
7.1.54 GCS—General Control and Status Register ............................................... 296
7.1.55 BUC—Backed Up Control Register ........................................................... 298
7.1.56 FD—Function Disable Register ................................................................ 299
7.1.57 CG—Clock Gating (Mobile/Ultra Mobile Only) ............................................ 301
8 LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only) ........................... 303
8.1 PCI Configuration Registers (LAN Controller—B1:D8:F0) ....................................... 303
8.1.1 VID—Vendor Identification Register (LAN Controller—B1:D8:F0) ................. 304
8.1.2 DID—Device Identification Register (LAN Controller—B1:D8:F0) ................. 304
8.1.3 PCICMD—PCI Command Register (LAN Controller—B1:D8:F0) .................... 305
8.1.4 PCISTS—PCI Status Register (LAN Controller—B1:D8:F0) .......................... 306
8.1.5 RID—Revision Identification Register (LAN Controller—B1:D8:F0) ............... 307
8.1.6 SCC—Sub Class Code Register (LAN Controller—B1:D8:F0) ........................ 307
8.1.7 BCC—Base-Class Code Register (LAN Controller—B1:D8:F0) ...................... 307
8.1.8 CLS—Cache Line Size Register (LAN Controller—B1:D8:F0) ........................ 308
8.1.9 PMLT—Primary Master Latency Timer Register (LAN Controller—B1:D8:F0)... 308
8.1.10 HEADTYP—Header Type Register (LAN Controller—B1:D8:F0) ..................... 308
8.1.11 CSR_MEM_BASE — CSR Memory-Mapped Base
Address Register (LAN Controller—B1:D8:F0)........................................... 309
8.1.12 CSR_IO_BASE — CSR I/O-Mapped Base Address Register
(LAN Controller—B1:D8:F0) ................................................................... 309
8.1.13 SVID — Subsystem Vendor Identification (LAN Controller—B1:D8:F0) ......... 309
8.1.14 SID — Subsystem Identification (LAN Controller—B1:D8:F0)...................... 310
8.1.15 CAP_PTR — Capabilities Pointer (LAN Controller—B1:D8:F0) ...................... 310
8.1.16 INT_LN — Interrupt Line Register (LAN Controller—B1:D8:F0).................... 310
8.1.17 INT_PN — Interrupt Pin Register (LAN Controller—B1:D8:F0) ..................... 311
8.1.18 MIN_GNT — Minimum Grant Register (LAN Controller—B1:D8:F0) .............. 311
8.1.19 MAX_LAT — Maximum Latency Register (LAN Controller—B1:D8:F0) ........... 311
8.1.20 CAP_ID — Capability Identification Register (LAN Controller—B1:D8:F0)...... 311
8.1.21 NXT_PTR — Next Item Pointer (LAN Controller—B1:D8:F0) ........................ 312
8.1.22 PM_CAP — Power Management Capabilities (LAN Controller—B1:D8:F0) ...... 312
8.1.23 PMCSR — Power Management Control/
Status Register (LAN Controller—B1:D8:F0)............................................. 313
8.1.24 PCIDATA — PCI Power Management Data Register
(LAN Controller—B1:D8:F0) ................................................................... 314
8.2 LAN Control / Status Registers (CSR) (LAN Controller—B1:D8:F0).......................... 315
8.2.1 SCB_STA—System Control Block Status Word Register
(LAN Controller—B1:D8:F0) ................................................................... 316
8.2.2 SCB_CMD—System Control Block Command Word
Register (LAN Controller—B1:D8:F0)....................................................... 317
8.2.3 SCB_GENPNT—System Control Block General Pointer
Register (LAN Controller—B1:D8:F0)....................................................... 319
Intel ® ICH7 Family Datasheet
11
Free Datasheet http://www.datasheet4u.net/

11 Page







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