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PDF SCI7500F0A Data sheet ( Hoja de datos )

Número de pieza SCI7500F0A
Descripción MLS Driver Chip Set
Fabricantes EPSON 
Logotipo EPSON Logotipo



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No Preview Available ! SCI7500F0A Hoja de datos, Descripción, Manual

SCI7500F0A
Free Datasheet http://www.datasheet4u.net/

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SCI7500F0A pdf
SCI7500F0A
Explanation of Block Diagram
q Liquid Crystal Drive Polarity Reverse Signal Generator Circuit
This circuit generates the reverse polarity signal FR from the 1H period pulse signal LP. Pins L0 to L3
can be used to set the polarity reversal interval to 2H to 17H. Moreover, so that it will be possible to
drive the top and bottom screens in a 2-screen drive panel in opposite phases, this IC outputs two signals
with opposite polarities of each other (FR, XFR).
q Timing Signal Generator Circuit
This circuit generates the clock for the charge pump from the 1H period pulse signal LP. When the
display off control signal XSLP is set to the VSS level, the clock stops and the voltage converter
operation stops.
q Column Driver Voltage Conversion Circuit
This circuit generates the V2, –V2, and –V3 voltage levels required for column driving.
q Row Driver Voltage Conversion Circuit
This generates the voltage (VEE) required for generating the power supply voltages (VH, VL) required
for the row drivers. Using VDD as the reference, this generates either a 5 × or 6 × voltage level in the
negative direction relative to the input power supply voltage. A terminal can be used to switch between
the step-up modes. The contrast adjustment function is performed through the use of an external emitter
follower circuit to adjust VEE to generate VL.
q Row Driver Logic Circuit Part Power Supply Voltage Generator Circuit
This generates the power supply voltage (VDDy) required by the row driver logic circuit part. This
generates a voltage that is higher than the voltage level VL by an amount equal to VDD–VSS.
q VH Voltage Generator Control Circuit
This is a circuit for generating the power supply voltage (VH) required for the row driver. The VH
voltage can be generated by an external MOS transistor and this circuit.
q VL Discharge Circuit
At power off or display off, this circuit discharges the charge remaining on the row driver negative
voltage level-side power supply voltage terminal (VL).
MLS Driver Chip Set
Technical Manual
EPSON
6–3
Free Datasheet http://www.datasheet4u.net/

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SCI7500F0A arduino
SCI7500F0A
The relationships between voltage levels in the system shown in Figure 2 are given in the table below.
6
5
4
3
2
VDD 1
VSS 0
-1
-2
-3
-4
-5
-6
VDD
VSS
[SED1360]
Controller
VH VH
VDD
VSS
V3
V2 V2
VC
–V2 –V2
–V3 –V3
VEM
VDDy VDDy
VL VL
VEE
[SCI7500]
Power Supply IC +
External Components
[SED1580]
Column
Driver
[SED1751]
Row Driver
Figure 3: The Relationships Between Voltages Within the System (in 6 × step-up mode)
The logical formulas for each of the voltage levels is as given below:
When in 6 × step-up mode
(when HC is connected to –V3B).
Logical Formula
Voltage level when
VDD = 3.0V
and VSS = 0V
VH = –VL = 5 (VDD–VSS)–α
15.0–α
V3 = VDD–VSS
3.0
V2 = 1/2 (VDD–VSS)
1.5
VC = VSS
0
–V2 = –1/2 (VDD–VSS)
–1.5
–V3 = –V3B = –(VDD–VSS)
–3.0
VEM = –3 (VDD–VSS)
–9.0
VDDy = –4 (VDD–VSS) + α
–12.0 + α
VL = –5 (VDD–VSS) + α
–15.0 + α
VEE = –5 (VDD–VSS)
–15.0
Where α = variable 0 (contrast adjustment)
When in 5 × step-up mode
(when HC is connected to VSS).
Logical Formula
Voltage level when
VDD = 3.0V
and VSS = 0V
VH = –VL = 4 (VDD–VSS)–α
12.0–α
V3 = VDD–VSS
3.0
V2 = 1/2 (VDD–VSS)
1.5
VC = VSS
0
–V2 = –1/2 (VDD–VSS)
–1.5
–V3 = –V3B = –(VDD–VSS)
–3.0
VEM = –2 (VDD–VSS)
–6.0
VDDy = –3 (VDD–VSS) + α
–9.0 + α
VL = –4 (VDD–VSS) + α
–12.0 + α
VEE = –4 (VDD–VSS)
–12.0
MLS Driver Chip Set
Technical Manual
EPSON
6–9
Free Datasheet http://www.datasheet4u.net/

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