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PDF 25P32 Data sheet ( Hoja de datos )
| Número de pieza | 25P32 | |
| Descripción | EN25P32 | |
| Fabricantes | Eon Silicon Solution | |
| Logotipo |  |
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EN25P32
32 Mbit Uniform Sector, Serial Flash Memory
EN25P32
FEATURES
• Single power supply operation
- Full voltage range: 2.7-3.6 volt
• 32 M-bit Serial Flash
- 32 M-bit/4096 K-byte/16384 pages
- 256 bytes per programmable page
• High performance
- 100MHz clock rate
• Low power consumption
- 5 mA typical active current
- 1 μA typical power down current
• Uniform Sector Architecture:
- Sixty four 64-Kbyte sectors
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
• High performance program/erase speed
- Byte program time: 7µs typical
- Page program time: 1.5ms typical
- Sector erase time: 800ms typical
- Chip erase time: 25 Seconds typical
• Lockable 512byte OTP security sector
• Minimum 100K endurance cycle
• Package Options
- 16 pins SOP 300mil body width
- 8 pins SOP 200mil body width
- 8 contact VDFN
- All Pb-free packages are RoHS compliant
• Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25P32 is a 32M-bit (4096K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25P32 is designed to allow either single Sector at a time or full chip erase operation. The
EN25P32 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/10/18
Free Datasheet http://www.datasheet4u.com/
1 page  
EN25P32
MEMORY ORGANIZATION
The memory is organized as:
z 4,194,304 bytes
z Uniform Sector Architecture
Sixty four 64-Kbyte sectors
z 16384 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or
Bulk Erasable but not Page Erasable.
Table 2 Block Sector Architecture
Sector
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
SECTOR SIZE (KByte)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Address range
3F0000h – 3FFFFFh
3E0000h – 3EFFFFh
3D0000h – 3DFFFFh
3C0000h – 3CFFFFh
3B0000h – 3BFFFFh
3A0000h – 3AFFFFh
390000h – 39FFFFh
380000h – 38FFFFh
370000h – 37FFFFh
360000h – 36FFFFh
350000h – 35FFFFh
340000h – 34FFFFh
330000h – 33FFFFh
320000h – 32FFFFh
310000h – 31FFFFh
300000h – 30FFFFh
2F0000h – 2FFFFFh
2E0000h – 2EFFFFh
2D0000h – 2DFFFFh
2C0000h – 2CFFFFh
2B0000h – 2BFFFFh
2A0000h – 2AFFFFh
290000h – 29FFFFh
280000h – 28FFFFh
270000h – 27FFFFh
260000h – 26FFFFh
250000h – 25FFFFh
240000h – 24FFFFh
230000h – 23FFFFh
220000h – 22FFFFh
210000h – 21FFFFh
200000h – 20FFFFh
1F0000h – 1FFFFFh
1E0000h – 1EFFFFh
1D0000h – 1DFFFFh
1C0000h – 1CFFFFh
1B0000h – 1BFFFFh
This Data Sheet may be revised by subsequent versions
5
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/10/18
Free Datasheet http://www.datasheet4u.com/
5 Page 
Table 5. Manufacturer and Device Identification
OP Code
(M7-M0)
(ID15-ID0) (ID7-ID0)
ABh 15h
90h 1Ch
15h
9Fh 1Ch 2016h
EN25P32
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and
Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction
code, and then driving Chip Select (CS#) High.
Write Disable (WRDI) (04h)
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip
Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#)
high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status
Register, Page Program, Sector Erase, and Bulk Erase instructions.
This Data Sheet may be revised by subsequent versions 11 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2007/10/18
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 25P32.PDF ] | |
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