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PDF SDA5642X Data sheet ( Hoja de datos )
| Número de pieza | SDA5642X | |
| Descripción | 1-Chip-VPS-Decoder | |
| Fabricantes | Siemens | |
| Logotipo |  |
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SDA 5642
SDA 5642X
1-Chip-VPS-Decoder
Preliminary Data
Features
µC suitable VPS data editing direct from CVBS signal
n-channel MOS
Generating of the line synchronous 5-MHz clock for
the time base and data clock by means of PLL operation
Very few external components necessary
Adaptative data separation
Frame signal recognition
Decoder for line 16
Bi-phase and start code checking
I2C-Bus interface
Operating voltage: 5 V
Video input signal level 1 … 2.0 Vpp
SDA 5642
SDA 5642X
MOS IC
P-DIP-14-1
P-DSO-20-1
Type
SDA 5642
SDA 5642X
Ordering Code
Q67100-H8547
Q67100-H8637
Package
P-DIP-14-1
P-DSO-20-1
Functional Description
The MOS circuit SDA 5642 is used to retrieve the required data for the Video Program System
(VPS) service from the data line No. 16 which is included in the CVBS signal. These data are
decoded according to the specification given in "Richtlinie ARD/ZDF Nr. 8 R 2".
This circuit incorporates the digital functions of the VPS decoder SDA 5640 and the analog
functions of the video processor SDA 5232 on one chip. Together with a reduced number of
external components this chip is a low cost solution for the VPS detector. The single chip
solution can retrieve the data from line 16 of the CVBS signal. These data are decoded,
checked for transmission errors and are stored in registers for further processing by a
microcontroller. The I2C-Bus interface is used for communication of a microcontroller with the
VPS-decoder.
The recording of programs by a VTR is controlled by the VPS label, a program related dataco-
de which accompanies each TV program during its transmission.
As a result the circuit prevents errors in the recording, as can be seen when using the timer
control, when programs are delayed, or are longer than expected.
Semiconductor Group
5
12.94
Free Datasheet http://www.datasheet4u.com/
1 page  
SDA 5642
SDA 5642X
Circuit Description
The function of this integrated circuit is to regenerate the biphase coded VPS data from the
CVBS signal. These data are transferred during line 16, which is part of the vertical blanking
time. After decoding and a check for transmission errors, these data can be acquired by a
microcontroller for further processing. The function of the circuit is explained in more detail by
means of the block diagram.
The CVBS signal (pos. video) from the IF-stage is coupled to the device by means of a
capacitor. The required level is typically 1 Vpp. Then the signal path is split into two parts:
In the synchronous pulse separator stage the CVBS signal is clamped, filtered and the video
signal is clipped away from the synchronization pulses. The output signal of this stage is VCS
signal. This is used as the control signal for the line 16 decoder and is also used for the
blanking of the color burst. This signal is also used in the regeneration of the internal clock
(PLL).
The second signal path leads to the data slicer. After amplification of the video signal the level
is averaged and the slicing level is derived from this signal. The slicing level is equal to one
half of the level difference between the minimum and the maximum value of the data signal.
This assures the optimal slicing of the data from the video signal.
The biphase coded data signal sliced from the video signal and the synchronization pulse
signal VCS are used in the clock generator circuit. Based upon a PLL, this circuit generates a
clock frequency of 5 MHz from the VCS signal. This clock signal is synchronized to the line
frequency. During line 16 the clock is synchronized to the data signal.
The synchronization of the data clock is controlled by the signal Z 16, which is the output of the
decoder for line 16. This decoder is used to detect line 16 from the VCS signal and to control
the data acquisition during this time. An indication signal for the first field of a frame is genera-
ted by measuring the duration of the VCS signal pulses and the interval between them.
The regenerated data signal and the recovered data clock are the input signals for a decoding
logic which performs the test for the start code and the biphase code. For this purpose the data
signal during line 16 is searched for the start bit. This bit, which is used for the synchronization
of the decoding logic, is the only bit which does not comply with the biphase format (Manche-
ster code). The detection of the startcode, which is contained in the next six bits following the
start bit, is required for the transfer of the correct data into the output register.
Among the 15 bytes (8 bits/byte), which are transferred by the data line 16, only 5 bytes are
important for the operation of VPS in the video recorder. These are the 5th and the 11th
through the 14th byte. These 40 bits in total are transferred into a serial operating register buf-
fer. The check for the correct transfer of the data according the biphase code is performed du-
ring the complete transfer of the data telegram in line 16. After the end of word 14 the relevant
bytes are transferred into the transmission register bank. This is done when a microcontroller
can read the data from the transmission register bank via the I2C-Bus interface. The device
can operate on the I2C-Bus as slave-transmitter device. After reading the data, all registers
are set to hex "F". Only after the correct reception of data line 16, is the register content up-
dated again.
1) the start code has been identified
2) the transmission was done correctly according to the biphase code format, and
3) if there is no concurrent access to the device via the I2C-Bus.
Semiconductor Group
9
Free Datasheet http://www.datasheet4u.com/
5 Page 
SDA 5642
SDA 5642X
Test Circuit
Data Line Receiver
Application Circuit
Data Line Receiver
Semiconductor Group
15
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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| PDF Descargar | [ Datasheet SDA5642X.PDF ] | |
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