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PDF BL35P02 Data sheet ( Hoja de datos )
| Número de pieza | BL35P02 | |
| Descripción | 8-Bit OTP MCU | |
| Fabricantes | SHANGHAI BELLING | |
| Logotipo |  |
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BL35P02 DATASHEET
8-bit OTP MCU
V 1. 0 ( 2010-4-6)
Shanghai Belling Co., Ltd.
Free Datasheet http://www.datasheet4u.com/
1 page  
上海贝岭股份有限公司
Shanghai Belling Co., Ltd.
6．Function Description
6.1 Instructions
See Section 7 for details on the instructions.
BL35P02 DATASHEET
6.2 Address Spaces
$0000-$000F：Control registers
$0010-$00DF：Reserved
$00E0-$00FF：RAM
$0100-$17FF：Reserved
$1800-$1FFF：OTP ROM
6.3 Crystal Oscillator
6.3.1 High frequency Oscillator
Simplified external crystal/ceramic oscillator circuits are shown in Figure 6.3.1.1. An external crystal or
ceramic oscillation source provides 355KHz~8MHz. The load capacitor Cx which values used in the oscillator
circuit design should include all stray capacitance is necessary, but frequency is more than 3.5MHz, Cx can be
removed. The crystal and components should be mounted as close as possible to the pins for start-up
stabilization and to minimize output distortion.
OSCI OSCO
Cx Cx
Frequency
8MHz
4MHz
3.64MHz
Value of Cx
0/15p
0/15p/30p
0/15p/30p
O scillator
Figure 6.3.1.1
6.3.2 455KHz Oscillator
Using 455KHz crystal/ceramic oscillation is shown Figure 6.3.2.1，generally OSCI/OSCO must be
connected external 200pF capacitor. Otherwise OSCO can be connected 2KΩ to 5KΩ resistor that can be
used by carbon film resistor.
TEL：86-21-64850700
Figure 6.3.2.1
WEB: www.belling.com.cn
Page 5 of 27
Free Datasheet http://www.datasheet4u.com/
5 Page 
上海贝岭股份有限公司
Shanghai Belling Co., Ltd.
Notice：
-: is undefined；
u: is unaffected.
MCR
$0C R/W
BL35P02 DATASHEET
00-0 0000
PA ($00): Port A Data Registers
.7-.0 PA[7:0]
When a Port A pin is programmed as an output the state of the corresponding data register bit
determines the state of the output pin.
When a Port A pin is programmed as an input, a read of the Port A Data Register will return the
logic state of the corresponding Port A pin.
DDRA($04): Port A Data Direction Registers
.7-.0 DDRA[7:0]
Port A pin may be programmed as an input or output by clearing or setting the corresponding bit
int DDRA.
0 (clear) - Port A pin is used as an input
1 (set) - Port A pin is used as output
PB ($02): Port B Data Registers
.7-.2,.0 PB[7:2,0]
When a Port B pin is programmed as an output the state of the corresponding data register bit
determines the state of the output pin.
When a Port B pin is programmed as an input, a read of the Port B Data Register will return the
logic state of the corresponding Port B pin.
DDRB($05): Port B Data Direction Registers
.7-.2 DDRB[7:2]
Port B pin may be programmed as an input or output by clearing or setting the corresponding bit
int DDRA.
0 (clear) - Port A pin is used as an input
1 (set) - Port A pin is used as output
.0 KBEB0 – PB0 Keyboard Interrupt Enable
KBEB0 is a keyboard Interrupt Enable bit of PB0 pin。
0 (clear) – Keyboard interrupt of PB0 pin disabled.
1 (set) - Keyboard interrupt of PB0 pin enabled. PB0 has no pull-up resistor.
TDR($08): Timer Data Register
The TDR is a read/write register which contains the current value of the 8-bit count-down timer
counter when read. Reading this register does not disturb the counter operation.
TCR($09): Timer Control Register
.7 TIF – Timer Interrupt Flag
0 (clear) – The timer has not reached a count of zero.
1 (set) - The timer has reached a count of zero.
The timer interrupt flag is set when the 8-bit counter decrements to zero. This bit is cleared on
reset, or by writing a “0” to the TIF bit.
.6 TIM – Timer Interrupt Mask
0 (clear) – Timer interrupt request to the CPU is not masked (enable).
1 (set) – Timer interrupt request to the CUP is masked (disable).
TEL：86-21-64850700
WEB: www.belling.com.cn
Page 11 of 27
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11 Page | ||
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| PDF Descargar | [ Datasheet BL35P02.PDF ] | |
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