|
|
PDF IDT7142LA Data sheet ( Hoja de datos )
| Número de pieza | IDT7142LA | |
| Descripción | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT7142LA (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
Features
◆ High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25ns (max.)
– Military: 25/35/55/100ns (max.)
◆ Low-power operation
– IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
HIGH SPEED
2K x 8 DUAL PORT
STATIC RAM
IDT7132SA/LA
IDT7142SA/LA
◆ MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
◆ On-chip port arbitration logic (IDT7132 only)
◆ BUSY output flag on IDT7132; BUSY input on IDT7142
◆ Battery backup operation —2V data retention (LA only)
◆ TTL-compatible, single 5V ±10% power supply
◆ Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
◆ Military product compliant to MIL-PRF-38535 QML
◆ Industrial temperature range (–40°C to +85°C) is available for
selected speeds
◆ Green parts available, see ordering information
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/OOL-I/O7L
BUSYL(1,2)
A10L
A0L
I/O
Control
I/O
Control
Address
Decoder
11
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
LOGIC
Address
Decoder
11
CER
OER
R/WR
I/OOR-I/O7R
m
BUSYR(1,2)
A10R
A0R
NOTES:
1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
IDT7142 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
2692 drw 01
©2015 Integrated Device Technology, Inc.
1
NOVEMBER 2015
DSC-2692/21
1 page  
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
7132SA
7142SA
7132LA
7142LA
Symbol
|ILI|
Parameter
Input Leakage Current(1)
Test Conditions
VCC = 5.5V,
VIN = 0V to VCC
Min. Max. Min. Max. Unit
___ 10 ___
5 µA
|ILO| Output Leakage Current
VOL Output Low Voltage
VCC = 5.5V,
CE = VIH, VOUT = 0V to VCC
IOL = 4mA
___ 10 ___
5
µA
___ 0.4 ___ 0.4 V
VOL Open Drain Output
Low Voltage (BUSY)
IOL = 16mA
___ 0.5 ___ 0.5
V
VOH Output High Voltage
IOH = -4mA
2.4 ___ 2.4 ___ V
NOTE:
1. At Vcc < 2.0V leakages are undefined.
2692 tbl 05
Data Retention Characteristics (LA Version Only)
Symbol
Parameter
Test Condition
VDR VCC for Data Retention
VCC = 2.0V
ICCDR Data Retention Current
CE > VCC -0.2V
Mil. & Ind.
VIN > VCC -0.2V or
Com'l.
tCDR(3)
Chip Deselect to Data Retention Time
VIN < 0.2V
tR(3) Operation Recovery Time
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
Min.
2.0
___
___
0
tRC(2)
Typ.(1)
___
100
100
___
___
Max.
___
4000
1500
___
___
Unit
V
µA
µA
ns
ns
2692 tbl 06
Data Retention Waveform
DATA RETENTION MODE
VCC
CE
4.5V
tCDR
VIH
VDR ≥ 2.0V
VDR
4.5V
tR
VIH ,
2692 drw 05
6.542
5 Page 
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(7,8)
7132X20(1)
7142X20(1)
Com'l Only
7132X25(2)
7142X25(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
BUSY Timing (For Master IDT7132 Only)
tBAA BUSY Access Time from Address
____ 20 ____ 20 ____ 20 ns
tBDA BUSY Disable Time from Address
____ 20 ____ 20 ____ 20 ns
tBAC BUSY Access Time from Chip Enable
____ 20 ____ 20 ____ 20 ns
tBDC BUSY Disable Time from Chip Enable
____ 20 ____ 20 ____ 20 ns
tWDD Write Pulse to Data Delay(2)
____ 50 ____ 50 ____ 60 ns
tWH Write Hold After BUSY(6)
12 ____ 15 ____ 20 ____ ns
tDDD Write Data Valid to Read Data Delay(2)
____ 35 ____ 35 ____ 35 ns
tAPS Arbitration Priority Set-up Time(3)
5 ____ 5 ____ 5 ____ ns
tBDD BUSY Disable to Valid Data(4)
____ 25 ____ 35 ____ 35 ns
BUSY Timing (For Slave IDT7142 Only)
tWB Write to BUSY Input(5)
0 ____ 0 ____ 0 ____ ns
tWH Write Hold After BUSY(6)
12 ____ 15 ____ 20 ____ ns
tWDD Write Pulse to Data Delay(2)
____ 40 ____ 50 ____ 60 ns
tDDD Write Data Valid to Read Data Delay(2)
____ 30 ____ 35 ____ 35 ns
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
2692 tbl 11a
Symbol
Parameter
Min. Max. Min. Max. Unit
BUSY Timing (For Master IDT7132 Only)
tBAA BUSY Access Time from Address
____ 30 ____ 50 ns
tBDA BUSY Disable Time from Address
____ 30 ____ 50 ns
tBAC BUSY Access Time from Chip Enable
____ 30 ____ 50 ns
tBDC BUSY Disable Time from Chip Enable
____ 30 ____ 50 ns
tWDD Write Pulse to Data Delay(2)
____ 80 ____ 120 ns
tWH Write Hold After BUSY(6)
20 ____ 20 ____ ns
tDDD Write Data Valid to Read Data Delay(2)
____ 55 ____ 100 ns
tAPS Arbitration Priority Set-up Time(3)
5 ____ 5 ____ ns
tBDD BUSY Disable to Valid Data(4)
____ 50 ____ 65 ns
BUSY Timing (For Slave IDT7142 Only)
tWB Write to BUSY Input(5)
0 ____ 0 ____ ns
tWH Write Hold After BUSY(6)
20 ____ 20 ____ ns
tWDD Write Pulse to Data Delay(2)
____ 80 ____ 120 ns
tDDD Write Data Valid to Read Data Delay(2)
____ 55 ____ 100 ns
NOTES:
1. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. 'X' in part numbers indicates power rating (SA or LA).
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
2692 tbl 11b
61.412
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet IDT7142LA.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT7142LA | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM | Integrated Device Technology |
| IDT7142LA | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM | Integrated Device Technology |
| IDT7142LA100C | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM | Integrated Device Technology |
| IDT7142LA100CB | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |